Re-driving CAwD and rD signal lines

Details Re-driving CAwD and rD signal lines Re-driving CAwD and rD signal lines

2005-07-29

2008-08-19

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S051000, C365S189050, C365S191000

Reexamination Certificate

active

07414917

ABSTRACT:
Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.

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