Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-10-06
2008-01-01
Tan, Vibol (Department: 2819)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S016000, C712S042000, C326S039000
Reexamination Certificate
active
07315933
ABSTRACT:
The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination operation unit if an accumulated process time is below an operation cycle allocated to the operation unit.The operation unit comprises at least a selector, a flip-flop and an operator. In a program for generating configuration information for switching the configuration of the operation unit of the re-configurable circuit, the selector selects the use
on-use of the flip-flop, based on the configuration information and selector switching condition is reflected in the configuration information for determining whether to take a route for transferring data inputted to the selector to the operator or a route for transferring the data to the operator skipping the flip-flop.
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Arent & Fox LLP
Tan Vibol
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