Coded data generation or conversion – Phase or time of phase change – Synchro or resolver signal
Reexamination Certificate
2011-08-23
2011-08-23
Williams, Howard (Department: 2819)
Coded data generation or conversion
Phase or time of phase change
Synchro or resolver signal
C324S207250
Reexamination Certificate
active
08004434
ABSTRACT:
An RD converter is disclosed that has a first multiplier multiplying a resolver signal S1by an output of a SIN ROM; a second multiplier multiplying a resolver signal S2by an output of a COS ROM; a subtractor subtracting an output of the first multiplier from an output of the second multiplier; a synchronous detecting circuit detecting synchronously an output of the subtractor with reference to an excitation signal; a controller controlling an output angle θ′ to make an output of the synchronous detecting circuit equal to zero; a correction data part outputting a correction angle θcfor the output angle θ′; an adder adding the output angle θ′ and the correction angle θc; the SIN ROM producing a sine value of a result from the adder; and the COS ROM producing a cosine value of the result.
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Office Action issued on Nov. 24, 2010 by the Japanese Patent Office for counterpart foreign patent application JP 2009-006909.
Extended European Search Report issued on Jan. 20, 2011 by the European Patent Office for counterpart foreign patent application EP 10 150 792.9.
S.K. Kaul, et al., “Improving the accuracy of low-cost resolver-based encoders using harmonic analysis,” Nuclear Instruments & Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Elsevier, Amsterdam, vol. 586, No. 2, Jan 7, 2008, pp. 345-355.
Nakazato Kenichi
Watanabe Masayuki
Japan Aviation Electronics Industry Limited
Lathrop David N.
Williams Howard
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