RC delay circuit for integrated circuits

Details RC delay circuit for integrated circuits RC delay circuit for integrated circuits

1997-07-14

1999-07-06

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327278, 327285, H03K 513

Patent

active

059202211

ABSTRACT:
This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition. The output of the delay circuit is fed back through the transistor capacitors to hasten the switching of the Schmitt trigger.

REFERENCES:
patent: 4707626 (1987-11-01), Inoue
patent: 5263000 (1993-11-01), Van Buskirk et al.
patent: 5479132 (1995-12-01), Verhaeghe et al.
patent: 5511026 (1996-04-01), Cleveland et al.
patent: 5767719 (1998-06-01), Furuchi et al.
patent: 5793238 (1998-08-01), Baker

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