Rationally clocked communication interface

Details Rationally clocked communication interface Rationally clocked communication interface

1992-08-12

1997-05-27

Kriess, Kevin A.

G06F 112

Patent

active

056340419

ABSTRACT:
An interface controlling digital communication between synchronous systems of unequal clock frequency. A phase locked loop generates one clock F.sub.m from the other F.sub.n by locking the phase of the two clocks at a beating period. Within the beating period, a precompiled set of valid and invalid communication clock cycles for each direction of communication are scheduled into lookup tables. The lookup tables generate outputs to a Set of registers for communicating data between the systems of unequal clock frequency.

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