Rational frequency division device and frequency synthesizer usi

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Patent

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Details

327115, 327117, 327156, 327158, H03L 706

Patent

active

058084932

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a rational number (rational) frequency division device and a frequency synthesizer using the same and, more particularly, to a rational frequency division device that can input an arbitrary rational number value and a frequency synthesizer that can output an output frequency signal corresponding to a non-integer multiple of a reference frequency with low spurious level using the rational frequency division device.


BACKGROUND ART

As is well known, a frequency synthesizer using a phase locked loop (PLL) circuit has a basic arrangement, as shown in FIG. 13 (note that the frequency division ratio to be input to a frequency divider 6 is only N (N: an integer)).
More specifically, in FIG. 13, a reference frequency signal a having a reference frequency f.sub.ref input from an input terminal 1 is input to a phase detector 2.
The phase detector 2 detects the phase difference between the reference frequency signal a and a frequency-divided signal b output from the frequency divider 6, and outputs a phase difference signal c having a voltage proportional to the phase difference.
The phase difference signal c output from the phase detector 2 is input to a loop filter 3 to remove its high-frequency component, and thereafter, is input as a new phase difference signal c.sub.1 to a voltage-controlled oscillator (VCO) 4.
The VCO 4 outputs an output frequency signal d having an output frequency f.sub.out corresponding to the signal value of the phase difference signal c.sub.1 to an output terminal 5.
Also, the output frequency signal d output from the VCO 4 is input to the frequency divider 6.
The frequency divider 6 divides the frequency of the output frequency signal d by an externally input frequency division ratio N (N: an integer), and supplies the result to the phase detector 2 as the frequency-divided signal b.
In such frequency synthesizer using the PLL circuit, the output frequency f.sub.out of the output frequency signal d output from the output terminal 5 is N times the reference frequency f.sub.ref, as described by the following equation:
In this equation, since N is an integer, the output frequency f.sub.out of the basic arrangement of the frequency synthesizer using the PLL circuit, as shown in FIG. 13, can only assume values corresponding to integer multiples of the reference frequency f.sub.ref.
When a low reference frequency f.sub.ref is set to decrease the step size of the output frequency f.sub.out, a problem of deterioration of the loop response characteristics of the PLL circuit or the like is posed.
In order to output an output frequency signal corresponding to a non-integer multiple of the reference frequency, a frequency synthesizer that adopts a fractional N scheme for obtaining the output frequency f.sub.out corresponding to a rational multiple of the reference frequency f.sub.ref has been proposed by U.S. Pat. No. 3,928,813.
More specifically, in the frequency synthesizer based on the fractional N scheme, the frequency division ratio to be set in the frequency divider 6 in the frequency synthesizer using the PLL circuit, as shown in FIG. 13, is switched from N to (N+1) at predetermined periods, as shown in FIG. 14.
For example, if the frequency division ratio N to be set in the frequency divider 6 is replaced by a frequency division ratio (N+1) at a rate of once in ten times, the output frequency f.sub.out as a whole assumes a f.sub.ref.
In this way, according to the frequency synthesizer based on the fractional N scheme, the output frequency f.sub.out corresponding to an arbitrary f.sub.ref is obtained, as defined by the following equation:
In this equation, N is an integer value, and J is a decimal value (a value below the decimal point) called a fractional value.
In the above-mentioned frequency synthesizer based on the fractional N scheme using the PLL circuit, when frequency modulation is performed in the PLL circuit, a modulation signal e having a frequency f.sub.m may be applied from an input terminal 8 to the input stage of the VCO 4 via

REFERENCES:
patent: 3913028 (1975-10-01), Bosselaers
patent: 3928813 (1975-12-01), Kingsford-Smith
patent: 4546331 (1985-10-01), DaSilva et al.
patent: 5038117 (1991-08-01), Miller
patent: 5305362 (1994-04-01), Miller
patent: 5602884 (1997-02-01), Wieczorkiewicz et al.
patent: 5694068 (1997-12-01), Rokugo

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