Ratioless type MIS logic circuit

Details Ratioless type MIS logic circuit Ratioless type MIS logic circuit

1977-03-04

1978-08-15

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307207, 307213, 307215, 357 23, 365104, H03K 1908, H03K 1920, G11C 1704

Patent

active

041075480

ABSTRACT:
A ratioless type MIS logic circuit comprises a logic block including at least one depletion mode FET inherently having a gate-to-source parasitic capacitance and a gate-to-drain parasitic capacitance, an output capacitance, a circuit for precharging the output capacitance and depletion mode clamping FETs connected one with each of the two ends of the logic block, the clamping FETs having their gates connected with a reference potential and the threshold voltage value of the FET in the logic block being larger than those of the clamping FETs.

REFERENCES:
patent: 3518451 (1970-06-01), Booher
patent: 3567968 (1971-03-01), Booher
patent: 3702945 (1972-11-01), Faith et al.
patent: 3866186 (1975-02-01), Suzuki
patent: 4016430 (1977-04-01), Kanezuka
patent: 4040015 (1977-08-01), Fukuda

Affiliated with

Also associated with

Rating

Ratioless type MIS logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ratioless type MIS logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ratioless type MIS logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1438143