Rate converting bit stream demultiplexer and multiplexer

Multiplex communications – Wide area network – Packet switching

Patent

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Details

370 84, H04J 302

Patent

active

043171982

ABSTRACT:
A rate converting bit stream demultiplexer and related multiplexer are disclosed. In the demultiplexer, there are two groups of N cascaded shift registers. A serial input data stream is alternately entered first into one of the groups of registers and then into the other. While the input data is being entered into one of the register groups, it is being simultaneously read from each shift register of the other group at a rate equal to the bit rate of the input data stream divided by N. In the multiplexer, the situation is reversed, with data being read from multiple input channels into each shift register in one group, while data is being read from a single output of the cascaded registers of the other group at a rate equal to N times the bit rate on the input channels.

REFERENCES:
patent: 3274340 (1966-09-01), Balderston et al.
patent: 3821480 (1974-06-01), Dundon et al.
patent: 3912872 (1975-10-01), Callens

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