Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate
1998-12-15
2004-05-18
Pham, Chi (Department: 2667)
Multiplex communications
Data flow congestion prevention or control
Control of data admission to the network
C370S419000, C370S395430, C370S464000
Reexamination Certificate
active
06738347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention introduces a communication apparatus designed for a constant bit rate communication and a method for securing a constant bit rate of transmission data to be transmitted over variable or constant bit rate communications networks. The variable bit rate communications network includes an Asynchronous Transfer Mode (ATM) network and the like over which various types of data travel in a fixed-length packet format, and the constant bit rate communications network includes telephone line networks, communication satellite circuit networks and the like.
2. Description of the Related Art
In the Asynchronous Transfer Mode (ATM) representing a data transmission technique implemented in a broadband Integrated Services Digital Network (ISDN), for example, various types of media data having different characteristics such as video data, audio data, information data and the like are transmitted in a uniform length cell format of 53 bytes. In the ATM network, data are allowed to be transmitted at any bit rate within a maximum transfer capacity of the network under the condition that a maximum output cell rate, an average cell rate and the like are to be declared. This type of communication with a communication bit rate varying with time is called a variable bit rate communication and another type with the communication bit rate being constant is called a constant bit rate communication.
In a network over which data are transferred in a cell format such as the ATM network and the like, there exists a transport time lag (referred to as “a delay variation” hereinafter) between transmitting and receiving stations so that a transmission timing of transmission data at a transmitting station cannot be used at a receiving station. Then, it has been a general practice of eliminating the delay variation that data transmitted on a constant bit rate basis are temporarily stored in a variation absorbing buffer at a receiving station so as to smooth over the variation.
Conventionally, a constant bit rate communication can be achieved by controlling a transmission interval of cells to be transmitted over the network from a line interface.
A conventional system for achieving a constant bit rate in data transmission is disclosed by Japanese Unexamined Patent Publication No. 212544/1992.
FIG. 18
shows a block diagram of an ATM packet adapter apparatus utilizing the rate control technique of the conventional system.
A conventional art to which the present invention is directed is discussed below with the conventional system being cited.
Referring to
FIG. 18
, an ATM packet adapter apparatus E
1
, transmission First-In First-Out (FIFO) units E
2
a
through E
2
d
, cell assembling units E
3
a
through E
3
d
, a call controller E
4
, a line interface (I/F) unit E
5
, terminals E
6
a
through E
6
b
with no ATM interface, a cell multiplexing bus E
7
, and a control bus E
8
within the ATM packet adapter apparatus E
1
(referred to as the control bus E
8
hereinafter) are shown. The transmission FIFO units E
2
a
through E
2
d
, the cell assembling units E
3
a
through E
3
d
, and the terminals E
6
a
through E
6
b
may be generically referred to, respectively, as a transmission FIFO unit E
2
, a cell assembling unit E
3
, and a terminal E
6
hereinafter.
The ATM packet adapter apparatus E
1
receives data from the terminal E
6
a
, E
6
b
, E
6
c
at the cell assembling unit E
3
b
, E
3
c
, E
3
d
, respectively, where the data are assembled to obtain cell data. The cell data are transferred to the transmission FIFO unit E
2
b
, E
2
c
, E
2
d
to be stored temporarily. Meanwhile, the call controller E
4
declares a maximum throughput of the data outputted from the terminal E
6
a
, E
6
b
, E
6
c
to an ATM switching system through a call control sequence. The transmission FIFO unit E
2
b
, E
2
c
, E
2
d
outputs the cell data according to a cell output interval being set based upon a maximum throughput determined by the call control sequence.
The call controller E
4
, upon reception of a call request from the terminal E
6
, declares a maximum throughput for the call request to the ATM network via the cell assembling unit E
3
a
, the transmission FIFO unit E
2
a
, the cell multiplexing bus E
7
and the Line I/F unit E
5
. When the maximum throughput is accepted, the call controller E
4
determines the maximum throughput as a maximum throughput for transmission.
The cell data from the terminals E
6
a
through E
6
c
outputted from the transmission FIFO units E
2
b
through E
2
d
are supplied to the multiplexing bus E
7
to be multiplexed, and multiplexed cell data are transferred to the line I/F unit E
5
for interfacing with the ATM network and transmitted over the ATM network.
FIG. 19
shows a block diagram illustrating the configuration of the transmission FIFO unit E
2
. Referring to the figure, an FIFO buffer E
9
stores cell data from the cell assembling unit E
3
temporarily, and an FIFO write controller E
11
and an FIFO readout controller E
12
control writing and reading, respectively, of the cell data in the FIFO buffer E
9
. The FIFO write controller E
11
, upon reception of the cell data from the cell assembling unit E
3
, detects the presence of the cell data and supplies a write signal WR to the FIFO buffer E
9
, and at the same time, supplies an FIFO data presence signal DP to a cell multiplexing bus controller E
13
. The cell multiplexing bus controller E
13
provided for an arbitration control of the cell multiplexing bus E
7
outputs a bus request (signal) BR to the cell multiplexing bus E
7
, and when receiving a bus grant (signal) BG in response, outputs a read start signal RDS to the FIFO readout controller E
12
.
A transmission interval controller E
10
provided in the transmission FIFO unit E
2
receives control information such as a set value for an input interval, the address data of the transmission FIFO unit E
2
, control data and the like from the call controller E
4
via the control bus E
8
.
The transmission interval controller E
10
controls the cell output interval of the cell data to be outputted to the cell multiplexing bus E
7
so as to have the interval being longer than the set value. The transmission interval controller E
10
includes a control bus I/F unit E
14
for interfacing with the control bus E
8
, a transmission interval setting register E
15
for latching the set value included in the control information, and a transmission interval counter E
16
for counting down from the set value as an initial value. The transmission interval counter E
16
outputs a count zero signal CZ indicating an end of counting to the cell multiplexing bus controller E
13
when a counting is completed.
FIG. 20
shows a block diagram illustrating the configuration of the transmission interval controller E
10
. The control bus I/F unit E
14
includes an address comparator E
17
and a control bus controller E
18
. The control bus E
8
here is assumed to include an eight-bit data bus for transmitting various types of control data, a 16-bit address bus for transmitting the address of each unit in the ATM packet adapter apparatus E
1
, and a control bus for transmitting a control signal (CS). The transmission interval controller E
10
receives at the transmission interval setting register E
15
a set value based upon a maximum throughput from the call controller E
4
via the data bus, an address via the address bus at the address comparator E
17
, and the control signal CS via the control bus at the control bus controller E
18
. The address comparator E
17
compares a received address with a self address to detect a matching of the received address with the self address of the transmission FIFO unit E
2
, and outputs a matching signal MS to the control bus controller E
18
when detecting the matching. The control bus controller E
18
, based upon the matching signal MS and the control signal CS, outputs a data latch signal DL to the transmission interval setting register E
15
. The transmission interval setting register E
15
latc
Mio Takeshi
Oka Susumu
Birch & Stewart Kolasch & Birch, LLP
Boakye Alexander O.
Mitsubishi Denki & Kabushiki Kaisha
Pham Chi
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