Rate adaption within a TDM switch using bit stuffing

Details Rate adaption within a TDM switch using bit stuffing Rate adaption within a TDM switch using bit stuffing

2008-05-13

2008-05-13

Ngo, Ricky Q. (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S235000, C370S429000

Reexamination Certificate

active

07372862

ABSTRACT:
The present invention discloses a method and an arrangement providing transmission of data through a node, e.g. a switch, having different input and output line interfaces in a wide range of data speed, without introducing any loss of bits, but still maintaining the nominal bit rate. This is achieved by means of a very simple and flexible implementation. At the receiving side of the switch, one extra bit per frame is transferred over the time slot bus of the switch if the number of bits in the corresponding FIFO of the input line exceeds a predefined upper limit. In contrast, one bit less per frame is transferred if the number of bits in the corresponding FIFO of the input line goes below a predefined lower limit. At the transmitting side of the switch, a FLL circuit regulates the data rate out of the FIFOs. The FLL circuit is implemented as a P-regulator having i.a. the fill degree of the FIFO as a direct input. Consequently, excellent jitter and frequency stability are achieved, and because of not using an I-component, the FLL circuit becomes stable.

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European Patent Office, International Search Report for PCT/NO02/00487 dated Mar. 11, 2003.

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