Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes
Reexamination Certificate
2001-11-16
2002-11-05
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from run length limited codes
C341S058000, C341S060000, C341S061000, C341S102000, C341S103000
Reexamination Certificate
active
06476737
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of high rate codes, and particularly to run-length limited modulation codes.
BACKGROUND OF THE INVENTION
This invention relates to coding techniques for use with magnetic storage media.
Write and read channels for magnetic storage devices often employ encoding and decoding of the sequence of bits that is to be stored on the magnetic device. Encoding of the symbols to be recorded onto the magnetic storage media can be used to increase the noise tolerance of the entire system.
Encoding, however, comes at a cost in that it expands the number of bits required to store a fixed amount of user source data on the disk. The rate of a code indicates the relationship between the number of bits of user data encoded and the number of bits of encoded data stored on the storage media.
The central problem, therefore, for any designer involves a trade-off between the coding rate used and the density of storage that may be achieved using any particular code. A modulation code for a partial response maximum likelihood (PRML) data recording and playback channel is selected to balance efficiency and robustness against errors. The efficiency of a code is measured by a code rate k
where k represents the number of user bits that are mapped into n recorded code bits by the encoder. Modulation codes with higher rates are deemed to be more efficient. Modulation codes which are more robust exclude more of the bit sequences that cannot be reliably detected. Thus, making the modulation code more robust results in a lower code rate. However, because detector performance can degrade with increasing channel densities, higher code rates are desirable.
Rate 8/9 (d=0, G=4/I=4) modulation codes have been used. Rate 16/17 (d=0, G=6/I=7) modulation codes have also been used. In the (d, G/I) run length limited (RLL) code constraints for use in magnetic recording of digital data in disk memory devices, parameters d and G are global constraints which represent the minimum and maximum of zero run lengths, respectively, in the interleaved code bit sequence.
The parameter I is the maximum interleave zero run length constraint. Because there may be consecutive 1s, the parameter d generally has a value of 0. A small value of G is desirable for accurate timing and gain recovery and control. These constraints must hold across codeword boundaries. Although described in terms of the (d, G/I) RLL code constraints for use in magnetic recording of digital data in disk memory devices, the code constraints and the apparatus for encoding and decoding data are applicable, however, to any PR signaling system employing ML detection.
Modulation codes have been employed within magnetic recording channels in order to achieve a more even distribution of magnetic flux transitions within a data track in view of data patterns of particular user information being encoded and recorded. In particular, RLL modulation codes have been employed within partial response, maximum likelihood sampling detection data recording and playback channels, as well as other detection channels.
A modulation code for a PRML data recording and playback channel is selected to impose certain signal playback conditions desired or needed to achieve robust and reliable data detection and to limit the span of information corrupted by errors in the recording/playback process, at the expense of some additional overhead information added to the coded data stream. The amount of additional overhead information directly relates to the rate (efficiency of the modulation code). The less overhead information added by the modulation code, the higher the rate or efficiency of the code. As efficiency increases less recording space is consumed by overhead information needed by the modulation code.
Magnetic storage systems typically include block memories and embedded control microprocessors. Currently, block memory arrays and control microprocessors used to handle data transfers within data storage systems are based upon 32 or 64 bit width bus architecture. As a consequence, the memory array's and the microprocessor's basic unit of data (data word) is 32 (or 64) bits.
Therefore, a hitherto unsolved need has remained for a very high rate modulation code for a magnetic recording channel which meets the foregoing requirements and solves the problems associated with the prior approaches.
There is a need for a high rate run-length limited modulation code with controlled error propagation.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a high rate run-length limited modulation code with controlled error propagation.
The invention presents a method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64 bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword, wherein the 65-bit codeword satisfies a predetermined minimum zero run length (d) constraint, a predetermined maximum zero run length (G) constraint, and a predetermined maximum interleave zero run length (I) coding constraint.
The purpose of the code of the present invention is twofold. First, through the G constraint, the code ensures that a transition occurs relatively frequently. This ensures that the timing and gain loops get information on which to operate. Second, it limits the length of certain sequences that, when they occur in an error event, can extend the length of that event indefinitely if not kept in check. Both the G and I constraints limit these patterns which can result in quasi-catastrophic error events.
The present invention describes a method for decoding a sequence of 65 bit encoded codewords into a sequence of 64-bit digital data word bits, comprising the steps of dividing the 65-bit encoded codeword into 5 11-bit intermediate blocks and 2 2-bit and 2 3-bit blocks of unconstrained and uncoded bits; decoding the five 11-bit intermediate blocks separately; decoding 17 bits of the 65-bit codeword to form two 8-bit bytes; and dividing each of the remaining 48 bits from both the five 11-bit intermediate blocks and the unconstrained and uncoded bits into six 8-bit bytes.
It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium such as a computer readable storage medium or a computer network wherein program instructions are sent over optical or electronic communication lines.
The present invention's 64/65 code provides a high rate. The present invention encodes 64 bit words, imparts (d=0, G=11/I=10) constraint onto data, and has manageable error propagation when used with 4-way interleave ECC and byte shuffling technique.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
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Altekar Shirish A.
Caroselli Joseph P.
MacDonald Charles E.
Nguyen Linh V
Suiter & Associates PC
Tokar Michael
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