Electrical pulse counters – pulse dividers – or shift registers: c – Pulse counting or dividing chains
Reexamination Certificate
2000-07-06
2002-08-06
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Pulse counting or dividing chains
C327S145000
Reexamination Certificate
active
06430250
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a digital timer comprising a binary counter driven by a counting clock signal, the counter presenting a stabilisation time after each counting pulse, and means for delivering a detection signal with a predetermined value when a counting order is reached.
2. Description of the Related Art
Digital timers are broadly used in electronic systems, in particular in microprocessors. Digital timers allow the generation of time bases of variable duration in function of a counting order N and a counting clock signal Hc, a detection signal being emitted when the counting order N is reached. The time between the starting of the timer and the emission of the detection signal is substantially equal to N×Tc, i.e. the product of the order N by the period Tc of the counting signal Hc.
With reference to
FIG. 1
, Timer
10
comprises a binary counter
1
, here a four bit counter, b
0
to b
3
. Counter
1
is driven by a counting clock signal Hc obtained by dividing, by means of a divider
6
, the frequency of a clock signal Hs delivered by an oscillator
7
. The output of counter
1
is applied to the input of a logic circuit
2
arranged for detecting a number N representing the counting order. The output of logic circuit
2
delivers an intermediate detection signal DS
1
applied to the input D of a synchronous type memory latch
4
, driven on its clock input CK by the clock signal Hs. The Q output of latch
4
delivers a detection signal DS
2
applied to the asynchronous control input “SET” (setting to 1) of another memory latch
5
, whose Q output delivers a detection flag DF.
FIGS. 2A
to
2
H illustrate the operation of timer
10
in the case where, for example, the order N is equal to
15
.
FIGS. 2A
to
2
D show respectively the values of the bits b
3
to b
0
during the counting steps of the numbers
13
to
15
.
FIGS. 2E
to
2
H show respectively the intermediate detection signal DS
1
, the clock signals Hc and Hs and the detection signal DS
2
.
Latch
4
samples the signal DS
1
with the rate of the clock signal Hs and the signal DS
2
copies the signal DS
1
at each rising edge of that signal. When the order N is reached by the output of counter
1
, the intermediate detection signal DS
1
changes its value and passes for example to 1. The logic value change of signal DS
1
, here its passage to 1, causes the passage to 1 of signal DS
2
and flag DF.
As well known by those skilled in the art, the passage to 1 or 0 of each bit b
0
to b
3
is performed with some delay in relation to each rising edge of the counting clock signal Hc, because of the logic signals' propagation time (or transistors' commutation time) in counter
1
. Therefore, the signal DS
1
presents a stabilization period Ti during which it may present an erroneous value, for example when counting the number
14
if the passage to 0 of the bit b
0
is performed with a little delay in relation to the passage to 1 of bit b
1
(FIG.
2
E). Consequently, the sampling of signal DS
1
by latch
4
at a moment when the signal DS
1
is erroneous would involve the emission of an erroneous detection signal DS
2
and a misleading up-date of flag DF at the output of latch
5
.
This drawback is solved in the prior art by off-setting the phase of the clock signals Hc and Hs so that the signal Hs passes to 1 some time after the signal Hc. Thus, as this appears in
FIGS. 2E
to
2
H, sampling latch
4
receives the rising edges of the signal Hs at moment Te when the signal DS
1
is stabilized.
However, this conventional solution has the drawback of delaying, for some fractions of period Tc, the emission of the detection signal DS
2
and the passage to 1 of the flag DF. In the best case, with a good adjustment of the phase of the clock signals Hc and Hs, the temporal delay is at least equal to the stabilization period Ti. However, in some applications, such a delay is not desirable and it is wished to provide a timer allowing the operation sequence with a better accuracy.
Another drawback of the conventional timer is that the clock signal Hs must not be too rapid compared to the data propagation time in the timer. More particularly, its period Ts must be greater than at least twice the duration of the stabilization period Ti of the counter, in order not to take the risk of sampling an erroneous signal DS
1
. The present invention is directed to avoid these drawbacks.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a digital timer which offers a great accuracy in the emission of the signal detecting the counting order.
Another object is to provide a digital timer whose accuracy is independent of the frequency of the clock signal Hs.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 3753127 (1973-08-01), Rowe
patent: 4499589 (1985-02-01), Geesen
patent: 4516861 (1985-05-01), Frew et al.
patent: 4596027 (1986-06-01), Bernardson
patent: 4692640 (1987-09-01), Suzuki et al.
patent: 5117173 (1992-05-01), Oliva et al.
patent: 5526391 (1996-06-01), Shankar et al.
patent: 1 188 135 (1965-03-01), None
Ferrand Olivier
Ruat Ludovic
Lam Tuan T.
STMicroelectronics SA
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