Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With bootstrap circuit
Reexamination Certificate
1999-04-12
2001-07-03
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With bootstrap circuit
C327S540000
Reexamination Certificate
active
06255900
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to on chip voltage generation techniques for producing a voltage on chip which is outside the range of a power supply voltage supplied to the chip; and more particularly to the generation of wordline voltages on low power memory devices like flash memory, mask ROM, and SRAM, where the power supply voltage may be less than the read potential required for sensing data in the memory.
2. Description of Related Art
Integrated circuits have in the past been manufactured in order to work with a power supply voltage of about 5 volts, within a specified range of +/−10%. Of course other power supply voltages have been utilized. There is a current trend for many applications to design integrated circuits to work with lower power supply voltages. Lower voltages generally result in lower power operation for the devices, and are easier to supply using batteries in small devices. For example, one low supply voltage which is emerging as a standard is specified to operate over a range of about 2.7 to 3.6 volts. Other standards are being developed around even lower voltages.
On chip circuits however are often designed to operate at higher voltages for some purposes. For example, in memory devices, such as flash memory, wordlines which supply a gate potential to memory cells are often designed to operate at a read potential of 4 volts or more. Thus, the low power supply voltage is insufficient to supply directly an on chip voltage high enough to drive the wordlines. This problem is dealt with by including charge pumps or other voltage supply boosters on the integrated circuits in order to supply the higher working voltages on chip. See for example U.S. Pat. No. 5,511,026 entitled BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES. The '026 patent describes an integrated circuit memory having charge pumps configured to supply wordline voltages at a level higher than the supply potential. Furthermore, the '026 patent describes the use of on chip charge pumps to provide a plurality of wordline voltages for multi-level/memory devices, so that a greater working margin is provided between the memory cell states, than would be normally available using a standard supply potential.
One problem associated with the prior art approaches to on chip charge pumps for these purposes arises from the difficulty of producing a well regulated output level without sacrificing speed. Well regulated levels are particularly important in multiple level per cell memory devices, or low voltage devices which operate with a narrow margin for the read voltage. However, it is desirable to read quickly. The time required to settle a charge pump output on a well regulated level can contribute a significant portion of delay to a read operation, or other operation requiring a charge pump generated output for operation.
Accordingly, it is desirable to provide a on chip voltage supply circuit for use with integrated circuits that provides for more precise control of the on chip voltage and which operates quickly.
SUMMARY OF THE INVENTION
The present invention provides an on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). According to one aspect of the invention, it can be characterized as an integrated circuit having a supply voltage input adapted to receive a supply potential within a pre-specified range of voltages, and including components on the integrated circuit that use an on chip voltage higher than the pre-specified range for the supply voltage. A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which after reaching the first threshold, boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably less than 2 nanoseconds of the transition in the boost signal.
According to one aspect of the invention, the detection circuit includes a first detector which supplies a first control signal to the voltage boost circuit within a first time interval of the node reaching the first threshold. During the first time interval, the voltage boost circuit continues boosting at the first rate. A second detector is coupled to the node, and supplies a second control signal to the voltage boost circuit within a second time interval of the node reaching the second threshold. During the second time interval, the voltage boost circuit continues boosting at the second rate, so that the on-chip voltage at the node increases less during the second time interval than during the first time interval. This slower increasing during the interval between the second detector detecting the second threshold, and the signaling of the voltage boost circuit, enables more precise control of the turn-off of the voltage boost circuit in response to the passing of the second threshold. This allows very fast boosting during the initial part of the pumping of the voltage in response to a single transition, while maintaining a precise cutoff.
According to other aspects of the invention, the voltage boost circuit comprises a capacitor, and a driving circuit coupled to one terminal of the capacitor. The driving circuit supplies the transition to the capacitor by supplying current at a first rate during the first mode, and supplying current at a second rate during the second mode. In one approach, the driving circuit comprises an inverter having an input connected to receive the boost signal and an output coupled to the capacitor. The inverter has first and second power supply terminals, and a current source coupled to one of the first and second power supply terminals having a first mode supplying current at the first rate, and a second mode supplying current at the second rate. In this way, the rate of increase of the voltage on the capacitor can be controlled in the first and second modes to establish the faster and slower rates of pumping.
According to another aspect of the invention, the voltage boosting circuit comprises a first stage and a second stage. The first stage includes a capacitor having a first and second terminals, a diode having an anode coupled to the second terminal capacitor and a cathode coupled to the node on the integrated circuit. A driver is coupled to the first terminal of the capacitor and supplies a first transition signal to the first capacitor. The second stage includes a second capacitor having a first terminal coupled to the node on the integrated circuit. A second driver is coupled to a second terminal of the second capacitor and supplies the transition of the boost signal to the second terminal of the capacitor according to the two modes of operation as discussed above.
In one aspect of the invention, the circuit also includes a first pre-charge circuit coupled to the anode of the diode in the first stage, and a second pre-charge circuit coupled to the cathode of the diode.
In addition, the circuit according to a preferred embodiment includes logic on the chip which is adapted to produce the first transition signal and the transition of the boost signal.
The present invention is particula
Chang Kuen-Long
Chen Ken-Hui
Ho Tien-Shin
Hung Chun-Hsiung
Lee I-Long
Haynes Mark A.
Haynes & Beffel LLP
Kim Jung Ho
Macronix International Co. Ltd.
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