Rapid bus priority resolution

Communications: electrical – Digital comparator systems

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G06F 300

Patent

active

039835405

ABSTRACT:
In a computer system wherein a number of peripheral devices contend with each other for access to a communication bus, a priority selection system is provided. The priority selection system includes priority address code setting means as a part of each of the peripheral devices. A contention bus is provided to which all of the peripheral devices are connected in parallel. Logic means are provided as a functional part of each of the peripheral devices. A logic means are responsive to the setting of the priority address codes to resolve the priority selection among the several contenders. With the logic means and the address code means being a part of the peripheral devices, the selection is independent of card cage slot position or of slot gaps. The system is also independent of the length of the communication bus.

REFERENCES:
patent: 3710324 (1973-01-01), Cohen et al.
patent: 3800287 (1974-03-01), Albright
patent: 3810114 (1974-05-01), Yamada et al.
patent: 3813651 (1974-05-01), Yamada
patent: 3815099 (1974-06-01), Cohen et al.
patent: 3909790 (1975-09-01), Shapiro et al.

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