Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-09-17
2004-12-14
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S169000, C382S181000, C714S736000
Reexamination Certificate
active
06831588
ABSTRACT:
FIELD OF THE INVENTION
The subject invention generally concerns the field of range recognizers for test and measurement instruments, such as logic analyzers, or the like, and specifically concerns a range encoder in an integrated circuit that provides more ranges or requires fewer connection pins.
BACKGROUND OF THE INVENTION
A range recognizer is a well-known circuit used in a logic analyzer trigger structures to identify input vectors that reside within a particular range of values. In such a range recognizer, two binary comparators are used to determine if an input vector lies between two predetermined boundaries. If data is sampled in more than one integrated circuit (IC or chip), the results produced by the comparators in a first one of the ICs must be passed to a second IC where it is combined with the results from second IC. This fact leads to the unfortunate situation that, the more range recognizers there are, the more IC pins and board space must be used.
A prior art range recognizer implementation used by Tektronix in the TLA 700 Logic Analyzer, requires twelve pins to convey signals to and from each of four range recognizers. That is, three pins per range recognizer are used to encode “greater than”, “lesser than”, or “equal to” the upper boundary and lower boundary.
As ICs become ever more complex, reduction of pin count and conservation of printed board space (commonly referred to a “real estate”) becomes critical. What is needed is a range recognizer that produces the desired range comparison signals while also reducing IC pin count and conserving printed board space.
SUMMARY OF THE INVENTION
A range recognizer arrangement in accordance with the subject invention, requires only five IC pins to convey an encoded signal from a group of four range recognizers, and requires only twelve IC pins to convey an encoded signal from a group of over one thousand range recognizers. The subject range recognizer arrangement includes circuitry for combining and monotonically sorting all of the predetermined range boundaries, rather than treating each range recognizer as a separate unit. A range recognizer arrangement in accordance with the subject invention is suitable for use with test and measurement instruments such as a logic analyzer or the like.
REFERENCES:
patent: 4237387 (1980-12-01), Devendorf et al.
patent: 4475237 (1984-10-01), Glasby
patent: 4692897 (1987-09-01), Crabbe, Jr.
patent: 4752928 (1988-06-01), Chapman et al.
patent: 5164728 (1992-11-01), Matsuzawa et al.
patent: 5579006 (1996-11-01), Hasegawa et al.
patent: 6590518 (2003-07-01), Taft
Jeanglaude Jean Bruner
Lenihan Thomas F.
Tektronix Inc.
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