Range count and main memory address accounting system

Details Range count and main memory address accounting system Range count and main memory address accounting system

1977-08-04

1980-05-20

Thesz, Joseph M.

Boots, shoes, and leggings

G06F 1300

Patent

active

042042500

ABSTRACT:
In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus for asynchronous intercommunication, an array of counters responsive to both hardware and firmware are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control.

REFERENCES:
patent: 3504345 (1970-03-01), Harmon et al.
patent: 3638195 (1972-01-01), Brender et al.
patent: 3665417 (1972-05-01), Low et al.
patent: 3668645 (1972-06-01), Reymond et al.
patent: 3727204 (1973-04-01), deKoe
patent: 3950735 (1976-04-01), Patel
patent: 3993981 (1976-11-01), Cassarino, Jr. et al.
patent: 3997878 (1976-12-01), Hirvela et al.

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