Random testing using scan path technique

Details Random testing using scan path technique Random testing using scan path technique

1983-12-01

1985-08-06

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

045340285

ABSTRACT:
A method is disclosed for testing a complex digital circuit that is designed as a serial access scan path. The circuit incorporates a number of flip-flops, at least some of which are selectively connectable into a scan path shift register. The circuit also has a number of primary inputs, primary outputs, a scan path input and a scan path output. In the testing method, a first digital test pattern is applied to the primary inputs and a second digital test pattern is shifted into the scan path shift register. The digits appearing at the primary outputs are repeatedly compared with those of a first digital number indicative of the proper operation of the circuit as each digit of the second digital test pattern is shifted into the scan path shift register. If the digits appearing at the primary outputs are not equal to those of the digital numbers to which they are compared, a signal indicative of faulty circuit operation is produced.

REFERENCES:
patent: 3376695 (1973-09-01), Eichelberger
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4340857 (1982-07-01), Fasang
patent: 4423509 (1983-12-01), Feissel
patent: 4493077 (1985-01-01), Agrawal et al.
T. W. Williams et al., Random Patterns Within a Structured Sequential Logic Design, 1977 Semiconductor Test Symposium, Cherry Hill, N.J., Oct. 1977, pp. 19-27.
"Built-in Test for Complex Digital Integrated Circuits" by Koenemann et al., IEEE Journal of Solid-State Circuits, vol. SC, No. 3, Jun. 1980, pp. 315-319.
J. H. Stewart, Application of Scan/Set for Error Detection and Diagnostics, 1978 Semiconductor Test Conference, Cherry Hill, N.J., Oct. 31-Nov. 2, 1978, pp. 152-158.

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