Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2011-03-29
2011-03-29
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
07916544
ABSTRACT:
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.
REFERENCES:
patent: 4785427 (1988-11-01), Young
patent: 5210434 (1993-05-01), Ohmi et al.
patent: 5544117 (1996-08-01), Nakayama et al.
patent: 5694356 (1997-12-01), Wong et al.
patent: 5751635 (1998-05-01), Wong et al.
patent: 6888571 (2005-05-01), Koshizuka et al.
patent: 7057936 (2006-06-01), Yaegashi et al.
patent: 7161830 (2007-01-01), Miwa et al.
patent: 2003/0151950 (2003-08-01), Tamada et al.
patent: 2005/0083726 (2005-04-01), Auclair et al.
patent: 2005/0162924 (2005-07-01), Guterman et al.
patent: 2005/0162940 (2005-07-01), Miwa et al.
Kurata, H., et al.;The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories; 2006 Symposium on VLSI Circuits Digest of Technical Papers; 2006 IEEE.
Bloom, I., et al.;l/f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation; Appl. Phys. Lett., vol. 58, No. 15,; Apr. 15, 1991; pp. 1664-1666.
Dierickx, B., et al.;The decrease of “random telegraph signal” noise in metal-oxide-semiconductor field-effect transistors when cycled from inversion to accumulation; J. Appl. Phys., vol. 71, No. 4, Feb. 15, 1992; pp. 2028-2029.
Imamlya, K., et al.;A 130MM2256 Mb NAND Flash with Shallow Trench Isolation Technology; Digest of Technical Papers; 1999 IEEE International Solid-State Circuits Conference; pp. 112-113, 152.
Bauer, M., et al.;A Multilevel-Cell 32Mb Flash Memory; Digest of Technical Papers; Solid-State Circuits Conference, 1995;IEEE International pp. 132-133, 351.
Ohsawa, T., et al.;Memory Design Using One-Transistor Gain Cell on SOI; ISSCC 2002, Feb. 5, 2002.
Gill, M, et al;Ovonic Unified Memory—A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications; Solid-State Circuits Conference, 2002, Digest of Technical Papers, ISSCC, 2002 IEEE International vol. 2, pp. 158-160.
Gogl, D., et al.;A 16-Mb MRAM Featuring Bootstrapped Write Drivers; IEEE Journal of Solid-State Circuits, vol. 40, No. 4, Apr. 2005, pp. 902-908.
Inoue, A., et al.;NAND Flash Applications Design Guide; System Solutions from Toshiba America Electronic Components, Inc., Revision 1.0, Apr. 2003.
Micro)n Technology, Inc.
Tran Michael T
Yoder Fletcher
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