Random pattern self test design

Details Random pattern self test design Random pattern self test design

1983-05-06

1985-10-08

Smith, Jerry

Excavating

371 15, H03K 19177

Patent

active

045464731

ABSTRACT:
A PLA is constructed to improve random testing. Section circuits are provided that permit disabling sections of the output lines that are called segments so that the circuit can be tested one segment at a time. Selection circuits are also provided for enabling the product term lines only one at a time. Thus, while random test signals are conventionally applied to the PLA input terminals for test, only a small portion of the PLA is enabled for the test. Control signals for the selection circuits are generated randomly so that the portion of the PLA that is tested is varied randomly.

REFERENCES:
patent: 3958110 (1976-05-01), Hong et al.
patent: 4418410 (1983-11-01), Goetze et al.
patent: 4435805 (1984-03-01), Hsieh et al.
patent: 4461000 (1984-07-01), Young
Fujiwara, A Design of PLAs with Universal Tests, IEEE Transactions on Circuits and Systems, Vol. CAS 28, No. 11, 11/81, pp. 1027-1032.
Eichelberger and Lindbloom, Random-Pattern Coverage Enhancement and Diag. for LSSD Logic & Self Test, IBM J. Res. Develop., vol. 27, No. 3, 5/83, pp. 265-272.
Wu, Pretesting Laserable PLA Peripheral Circuits, IBM Technical Disclosure Bulletin, vol. 22, No. 5, 10/79, pp. 1866-1869.
Daehn et al., A Hardware Approach to Self-Testing of Large PLAs, IEEE Trans. on Circuits & Systems, vol. CAS-28, No. 11, 11/81, pp. 1033-1037.

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