Random number generator circuit

Details Random number generator circuit Random number generator circuit

1988-10-28

1990-02-27

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 102

Patent

active

049051768

ABSTRACT:
A very large scale integrated (VLSI) compatible, random number generator which is highly invulnerable to cryptographic attack. The invulnerability to cryptographic attack is based upon a low frequency sampling of the output of a pseudo-random number generator which is operated at a varying frequency from a free-running ring oscillator. In a first embodiment, a free-running ring oscillator is used to drive a sampled linear feedback shift register. The asynchronous, serial pseudo-random number output from the linear feedback shift register is sampled periodically, thereby introducing randomly occurring deviations from the pseudo-random number sequence. A variation of the free-running ring oscillator is employed as the pseudo-random number generator, by introducing into the feedback loop of the ring oscillator, an exclusive OR circuit which is connected so that the ring oscillator thereby produces a serial, pseudo-random number sequence. Additional uncertainty in the sequence of random numbers produced by the free-running pseudo-random number generator, is caused by the race condition which occurs at the inputs to the exclusive OR connected in the circuit.

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F. J. MacWilliams, et al., "Pseudo-Random Sequences and Arrays," Proceedings of the IEEE, vol. 64, No. 12, 12/76, pp. 1715-1730.
"Integrated Circuit Compatible Ramdom Number Generator," IBM TDB, Apr. 1988, pp. 333-335.

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