Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-12-12
2006-12-12
Chaki, Kakali (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07149764
ABSTRACT:
A filtering apparatus in a hardware random number generator that prevents the random number generator (RNG) from outputting a contiguous string of zeros or ones longer than a specified length. The maximum length is programmable in the apparatus. The apparatus includes a counter that keeps a current count of contiguous zero bits in a series of bytes generated by the RNG. An adder generates a sum of the current zero bit count and the number of leading zeros in the next byte generated. If the sum exceeds the maximum length, then the filter throws out the byte rather than accumulating it. Otherwise, if the byte contains all zeros, the counter is updated with the sum; or if the byte contains trailing zeros, the counter is updated with the number of trailing zeros; otherwise the counter is cleared. The apparatus does the same for contiguous one bits.
REFERENCES:
patent: 3706941 (1972-12-01), Cohn
patent: 4063220 (1977-12-01), Metcalfe et al.
patent: 4375620 (1983-03-01), Singer et al.
patent: 4513386 (1985-04-01), Glazer
patent: 4780814 (1988-10-01), Hayek
patent: 5163132 (1992-11-01), DuLac et al.
patent: 5251165 (1993-10-01), James, III
patent: 5257282 (1993-10-01), Adkisson et al.
patent: 5446683 (1995-08-01), Mullen et al.
patent: 5528526 (1996-06-01), Klug et al.
patent: 5532695 (1996-07-01), Park et al.
patent: 5757923 (1998-05-01), Koopman, Jr.
patent: 6160755 (2000-12-01), Norman et al.
patent: 6199156 (2001-03-01), Yoder et al.
patent: 6247082 (2001-06-01), Lo et al.
patent: 6442579 (2002-08-01), Hansson
patent: 6594680 (2003-07-01), Gu et al.
patent: 6643740 (2003-11-01), Auracher
patent: 6816876 (2004-11-01), Jha et al.
patent: 6871206 (2005-03-01), Henry et al.
patent: 6947960 (2005-09-01), Hars
patent: 2001/0056534 (2001-12-01), Roberts
patent: 2002/0124032 (2002-09-01), Karp
patent: 2002/0172359 (2002-11-01), Karkku-Juhani
patent: 2003/0131217 (2003-07-01), Henry et al.
patent: 2003/0149863 (2003-08-01), Henry et al.
patent: 2003/0158876 (2003-08-01), Hars
patent: 2004/0019619 (2004-01-01), Buer et al.
patent: 2004/0019798 (2004-01-01), Koji
patent: 2004/0096060 (2004-05-01), Henry et al.
patent: 2004/0098429 (2004-05-01), Henry et al.
patent: 2004/0103131 (2004-05-01), Henry et al.
patent: 2004/0158591 (2004-08-01), Crispin
patent: 0172405 (1986-02-01), None
patent: 0285310 (1988-10-01), None
patent: 0415862 (1991-03-01), None
patent: 04140828 (1992-05-01), None
patent: 2003108365 (2003-04-01), None
patent: WO9914881 (1999-03-01), None
patent: WO 02/01328 (2002-01-01), None
Federal Information Processing Standard Publication, FIPS PUB 140-2, Security Requirements for Cryptographic Modules, May 25, 2001, Gaithersburg, MD.
Intel 82802AB/82802AC Firmware Hub (FWH), Nov. 2000, Document No. 290658-004.
Benjamin Jun, The Intel Random Number Generator, Cryptography Research, Inc. White Paper Prepared for Intel Corporation, Apr. 22, 1999.
IA-32 Intel Architecture Software Developer's Manual, vol. 2: Instruction Set Reference, 2001 pp. 3-114 to 3-127, 3-670 to 3-671, 3-785 to 3-786.
Atmel Secure Microcontroller for Smart Cards AT05SC3208R, Data Sheet, pp. 1-2, XP002288710 Section “Peripherals”.
Gammel B M: Hurst's rescaled range statistical analysis for pseudorandom number generator used in physical simulations: Physical review E, vol. 58, No. 2, Aug. 1998 (1998008) pp. 2586-2597, XP00228808 *p. 2589. ;left-hand column, line 4-line 12.
Rukhin AA Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic ApplicationsNIST Special Publication, Gaithersburg, MD, US. No. 800-822, May 15, 2001, XP002276676 ISSN: 1048-776X.
Analog Devices ADSP-2141L Safe Net DSP datasheet, Rev. 0, Analog Devices, Inc. 2000. Norwood, MA.
Trichina et al. “Supplemental Cryptographic Hardware for Smart Cards,”IEEE Micro. Nov.-Dec. 2001, pp. 26-35.
Ancona et al. “Parallel VLSI Architectures for Cryptographic Systems,”IEEE. 1997, pp. 176-181.
Henry G. Glenn
Parks Terry
Chaki Kakali
Davis E. Alan
Do Chat C.
Huffman James W.
IP-First LLC
LandOfFree
Random number generator bit string filter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Random number generator bit string filter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Random number generator bit string filter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3714844