Random logic error detecting system for differential logic netwo

Details Random logic error detecting system for differential logic netwo Random logic error detecting system for differential logic netwo

1984-12-24

1987-01-20

Atkinson, Charles E.

Excavating

371 57, G01R 3128

Patent

active

046384820

ABSTRACT:
A system for testing a differential logic network is provided which includes a differential exclusive OR circuit having a plurality of inputs for receiving complementary signals from the differential logic network and first and second output terminals and means, e.g., a conventional exclusive OR circuit, for determining the voltage difference between the first and second output terminals to indicate the presence or absence of a fault or error in the differential logic network under test.

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E. F. Hahn et al, IBM Technical Disclosure Bulletin, vol. 25, No. 2, Jul. 1982, p. 709, "VLSI Testing by On-Chip Error Detection".

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