Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2011-08-16
2011-08-16
Rodriguez, Paul L (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
Reexamination Certificate
active
08000950
ABSTRACT:
Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set.
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Hira Kalpesh
Panchal Neil A.
Baca Matthew W.
Guill Russ
International Business Machines - Corporation
Musgrove Jack V.
Rodriguez Paul L
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