Random carry-in for floating-point operations

Details Random carry-in for floating-point operations Random carry-in for floating-point operations

2004-10-22

2009-02-17

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S497000

Reexamination Certificate

active

07493357

ABSTRACT:
A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

REFERENCES:
patent: 5276634 (1994-01-01), Suzuki et al.
patent: 6167420 (2000-12-01), Saishi et al.
patent: 6269385 (2001-07-01), Han et al.

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