Random access MOS/memory cell with capacitor and transistor form

Details Random access MOS/memory cell with capacitor and transistor form Random access MOS/memory cell with capacitor and transistor form

1984-08-14

1986-09-23

James, Andrew S.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 236, 357 55, 365182, H01L 2978, G11C 1134

Patent

active

046138897

ABSTRACT:
A cell design for an MOS random access memory is disclosed. Two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitors and another for the gates of the MOS transistors and as the bit select line or to connect the gates to the bit select line. The bit select or X address line may overlie both the first and/or second level poly, so space is saved in the cell layout. A "V-groove" anisotropically etched storage capacitor may include the MOS access transistor in one end, formed by double implant.

REFERENCES:
patent: 4199772 (1980-04-01), Natori

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