Random access memory with page addressing mode

Details Random access memory with page addressing mode Random access memory with page addressing mode

1990-10-22

1993-09-14

Popek, Joseph A.

Static information storage and retrieval

Addressing

Byte or page addressing

36523002, 36518905, G11C 1300

Patent

active

052455858

ABSTRACT:
In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.

REFERENCES:
patent: 4567579 (1986-01-01), Patel et al.
patent: 4586167 (1986-04-01), Fujishima et al.

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