Static information storage and retrieval – Addressing – Sync/clocking
Patent
1995-06-07
1998-09-15
Yoo, Do Hyun
Static information storage and retrieval
Addressing
Sync/clocking
36523006, 36523008, 365236, G11C 800
Patent
active
058089586
ABSTRACT:
A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
REFERENCES:
patent: 4394753 (1983-07-01), Penzel
patent: 4429375 (1984-01-01), Kobayashi et al.
patent: 4581721 (1986-04-01), Gunawardana
patent: 4618947 (1986-10-01), Tran et al.
patent: 4649511 (1987-03-01), Gdula
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5093807 (1992-03-01), Hashimoto
patent: 5117393 (1992-05-01), Miyazawa et al.
patent: 5151881 (1992-09-01), Kajigaya et al.
patent: 5179670 (1993-01-01), Farmwald et al.
patent: 5226011 (1993-07-01), Yanagisawa
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5400288 (1995-03-01), Hashimoto et al.
T. Mori et al, "55 nsec, 1.3 Mb Video Memory With Rectangular Access for Graphic Systems", Electronic Information Communication Institute Technological Research Report, vol. 89, No. 69, DRAM 20 Proceeding Technology, pp. 49-54 (4740), ICD 89 26-40, Jun. 2, 1989, EIC Electronic Information Communication Institute Cooperated (Japanese translation included).
Reese, Ed and Eddy Huang, A Sub-10nS Cache SRAM for High Performance 32 Bit Microprocessors, IEEE, 1990 Cust. IC Confr., pp. 24.2.1-24.2.4.
Wilson, Ron, Will the Search for the Ideal Memory Architecture Ever End?, Computer Design, Jul. 1, 1990, pp. 78-99.
Hochstedler, Charles, Self-Timed SRAMs Pace High-Speed ECL Processors, Semiconductor Memories, 1990, pp. 4-10.
Lineback, J. Robert, Systems Snags Shouldn't Slow the Boom in Fast Static RAMS, Electronics, Jul. 23, 1987, pp. 60-62.
Triad Semiconductors Inc., Static RAMs have on-chip address and Data Latches for Pipelining, EDN, Dec. 8, 1988, p. 116.
Cole, Bernard C., Motorola's Radical SRAM Design Speeds Systems 40%, Electronics, Jul. 23, 1987, pp. 66-68.
Iqbal, Mohammad Shakaib, Internally Timed RAMs Build Fast Writable Control Stores, Electronic Design, Aug. 25, 1988, pp. 93-96.
Leibson, Steven, SRAMs' On-Chip Address and Data Latches Boost Throughput in Pipelined Systems, EDN, Oct. 13, 1988, pp. 102-103.
M. Hashimoto, et al., Proc. IEEE, Custom IC Confr., May 4-7, 1987, pp. 315-318.
M. Hashimoto et al., Proc. IEEE, vol. 23, No. 2, Apr. 1988, pp. 490-499.
Gallant, John, Special-feature SRAMs, EDN, Jun. 20, 1991, pp. 104-112/.
Weber, Samuel, Specialty SRAMs Are Filling the Speed Gap, Electronics, May 1990, pp. 85-87.
Balistreri Anthony Michael
Guttag Karl M.
Hartigan Joseph P.
Krueger Steven D.
Le Duy-Loan T.
Donaldson Richard L.
Rountree Robert N.
Telecky J. Fred
Texas Instruments Incorporated
Yoo Do Hyun
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