Random access memory with error correction capability

Details Random access memory with error correction capability Random access memory with error correction capability

1985-11-08

1987-12-01

Smith, Jerry

Excavating

371 51, G11C 2900, G06F 1110

Patent

active

047109343

ABSTRACT:
A Random Access Memory with error detection/correction capability includes an information array (10) for storage of a collective data word in a single row thereof and a parity array (12) for storage of corresponding parity information in a single row thereof. A single row of the information array (10) and the parity array (12) are accessed and input to an error correct circuit (54). The collective data and parity information are also input to an error syndrome/parity generator (48), the output of which is input to the error correct circuit (54) to correct bits that are in error. A latch (72) is provided for latching the corrected information therein to allow new data to be written therein. The output of the latch (72) is multiplexed into the error syndrome/parity generator (48) which is configurable as a parity generator to generate new parity information for a write operation. The new collective data and parity information in the write mode are stored in arrays (10) and (12).

REFERENCES:
patent: 4335458 (1982-06-01), Krol
patent: 4335459 (1982-06-01), Miller
patent: 4394763 (1983-07-01), Nagano
patent: 4456996 (1984-06-01), Haas
patent: 4542454 (1985-09-01), Brcich

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