Random access memory with divided memory banks and data read/wri

Details Random access memory with divided memory banks and data read/wri Random access memory with divided memory banks and data read/wri

1995-12-27

2000-09-12

Phan, Trong

Static information storage and retrieval

Addressing

Plural blocks or banks

36523008, G11C 800

Patent

active

061187216

ABSTRACT:
A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are subdivided into subgroups each of which has four memory cells. A first set of input/output lines is provided for the first group of memory cells, and a second set of input/output lines is provided for the second group of memory cells. An output circuit section is connected to the those sets of input/output lines to output data transferred thereto. An access controller section specifies subgroups alternately from the first and second groups of memory cells with four memory cells as a substantial access minimum unit, accesses memory cells of a specified subgroup to read stored data therefrom and transfers the read data to corresponding input/output lines associated therewith. The read data is supplied to the output circuit section for conversion to serial data and then output therefrom.

REFERENCES:
patent: 4130900 (1978-12-01), Watanabe
patent: 4498155 (1985-02-01), Mohan Rao
patent: 4630230 (1986-12-01), Sundet
patent: 4646270 (1987-02-01), Voss
patent: 4663742 (1987-05-01), Andersen et al.
patent: 4683555 (1987-07-01), Pinkham
patent: 4725945 (1988-02-01), Kronstadt et al.

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