Random access memory with digital signals running over the small

Details Random access memory with digital signals running over the small Random access memory with digital signals running over the small

1994-03-09

1995-10-10

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365 51, 365 69, G11C 506

Patent

active

054576482

ABSTRACT:
A novel semiconductor memory having a plurality of storage devices arranged in and X-Y array wherein the Input and Output data lines of the array are routed over a portion of the memory array. The Input and Output data lines are routed symmetrically between and in parallel with the small-signal bit-line pairs of the array which access the individual storage devices. The individual bit-lines of a bit-line pair cross-over one another at the midpoint of the portion of the array over which the Input and Output lines am routed. Buffers are included on the Input and Output lines at the periphery of the array in order to prevent noise external to the array from being transmitted into the array on the I/O data lines above the array. Output buffers are also provided to drive output data out across the array. Additionally, circuitry is provided for preventing the Input and Output lines from transitioning while small-signals are being developed on the bit-line pairs.

REFERENCES:
patent: 4916661 (1990-04-01), Nawoki et al.
patent: 5014241 (1991-05-01), Asakura et al.
patent: 5214601 (1993-05-01), Hidaka et al.
patent: 5280441 (1994-01-01), Wada et al.

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