Random access memory system for extending the memory addressing

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G06F 1306

Patent

active

043464416

ABSTRACT:
A logic memory addressing system requiring minimal central processing unit (CPU) control is provided for extending the memory addressing capacity of a CPU. A logic control system simplistic in design and including a logic decoding unit responds to control words issued by the CPU by way of control and address busses to randomly access memory words, and to effect the exchange of information between the memory unit and a data bus.

REFERENCES:
patent: 3818459 (1974-06-01), Vrablik
patent: 4056848 (1977-11-01), Gilley

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