Static information storage and retrieval – Addressing
Patent
1984-06-25
1986-07-01
Fears, Terrell W.
Static information storage and retrieval
Addressing
365189, 365175, G11C 1300, G11C 1140
Patent
active
045983909
ABSTRACT:
The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array preferably employing unclamped CTS (Complementary Transistor Switch) type memory cells.
REFERENCES:
patent: 3423737 (1969-01-01), Harper
patent: 3525084 (1970-08-01), Dunlop
patent: 3582911 (1968-06-01), Smith
patent: 3623033 (1971-11-01), Harding
patent: 3636377 (1972-01-01), Economopoulos
patent: 3736574 (1973-05-01), Gersbach
patent: 3753008 (1973-08-01), Guanaschelli
patent: 3771147 (1973-11-01), Boll
patent: 3786442 (1974-01-01), Alexander
patent: 3789243 (1974-01-01), Donofrio
patent: 3843954 (1974-10-01), Hansen
patent: 3863229 (1975-01-01), Gersbach
patent: 3919566 (1975-11-01), Millhollan
patent: 3942160 (1976-03-01), Yu
patent: 4007451 (1977-02-01), Heuber
patent: 4042915 (1977-08-01), Reed
patent: 4078261 (1978-03-01), Millhollan
patent: 4090254 (1978-05-01), Ho
patent: 4090255 (1978-05-01), Berger
patent: 4104735 (1978-08-01), Hofmann
patent: 4172291 (1979-10-01), Owens
patent: 4174541 (1979-11-01), Schmitz
patent: 4194130 (1980-03-01), Moench
patent: 4200918 (1980-04-01), Glock
patent: 4242605 (1980-12-01), Seelbach
patent: 4264828 (1981-04-01), Perlegos
patent: 4287575 (1981-09-01), Eardley
patent: 4308595 (1981-12-01), Houghton
patent: 4322820 (1982-03-01), Toyoda
patent: 4323986 (1982-04-01), Malaviva
patent: 4326270 (1982-04-01), Owens
patent: 4330853 (1982-05-01), Heimeier
patent: 4413191 (1983-11-01), Houghton
patent: 4417159 (1983-11-01), Dorler
patent: 4417326 (1983-11-01), Toyoda
"Static Cell Array Circuit to Enable Write by Turning Off the Cell Load Devices" by D. B. Eardly, IBM Technical Disclosure Bulletin, vol. 24, No. 6, Nov. 1981, p. 3044.
"AC Write Scheme for Bipolar Random-Access Memories Using Schottky Coupled Cells" by J. A. Dorler, J. M. Mosley, R. O. Seeger and J. R. Struk, IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, p. 4960.
"Constant Voltage, Current Sensing Circuit" by V. Marcello, A. P. Mercer, C. G. Rivadeneira and J. R. Struk, IBM Technical Disclosure Bulletin, vol. 24, No. 1B, Jun. 1981, p. 483.
"Tri-State Read/Write Control Circuit" by V. Marcello, C. G. Rivadeneira and J. R. Struk, IBM Technical Disclosure Bulletin, vol. 24, No. 1B, Jun. 1981, p. 480.
"Read/Write Control Circuit Reference Voltage Generator" by V. Marcello, C. G. Rivadeneira and J. R. Struk, IBM Technical Disclosure Bulletin, vol. 24, No. 1B, Jun. 1981, p. 478.
"Bit Current Steering Network" by V. Marcello, C. G. Rivadeneira and J. R. Struk, IBM Technical Disclosure Bulletin, vol. 24, No. 1B, Jun. 1981, p. 475.
"Complementary Transistor Switch Memory Cell" by J. A. Dorler, R. M. Esposito and S. Ogawa, IBM Technical Disclosure Bulletin, vol. 16, No. 12, p. 3931.
"Memory Cell" by S. K. Wiedmann, IBM Technical Disclosure Bulletin, vol. 13, No. 3, Aug. 1970, p. 616.
"A 1024 Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell", by J. A. Dorler, J. M. Mosley, G. A. Ritter, R. O. Seeger and J. R. Struk, IBM Journal of Research and Development, vol. 25, No. 2, May 1981, p. 126.
"Bit Driver and Select Circuit for Schottky-Coupled Cell Arrays" by C. U. Buscaglia and L. E. Knepper, IBM Technical Disclosure Bulletin, vol. 24, No. 10, Mar. 1982, p. 5167.
"Low Power Write Circuit for Fast VLSI Arrays" by R. D. Dussault, W. S. Homa and R. O. Seeger, IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, p. 5630.
"Read/Write Scheme for Bipolar Random-Access Memories Using Schottky Coupled Cells" by R. D. Dussault and W. S. Homa, IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, p. 5632.
DeBruin Wesley
Fears Terrell W.
International Business Machines - Corporation
LandOfFree
Random access memory RAM employing complementary transistor swit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Random access memory RAM employing complementary transistor swit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Random access memory RAM employing complementary transistor swit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1085967