Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-01-27
2001-07-17
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230050, C365S233500, C365S189040, C365S189050, C365S189120
Reexamination Certificate
active
06262936
ABSTRACT:
The invention described and claimed in this application may be related to copending application entitled, “Random Access Memory Having Read/Write Address Bus and Process For Writing To and Reading From The Same,” filed in the U.S. Patent and Trademark Office as a provisional patent application No. 60/078,029 on Mar. 13, 1998, by Cathal G. Phelan, Mathew R. Arcoleo, Ashish Pancholy, and Simon J. Lovett, incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
This invention relates generally to the field of semiconductor and/or integrated circuit devices, and more particularly to a random access memory and process for writing to and reading from the same.
SUMMARY OF THE INVENTION
The primary object of the invention is to provide a random access memory that increases data throughput.
Another object of the invention is to provide such a random access memory that may have either synchronous or asynchronous operation.
Another object of the invention is to provide a random access memory and method of operating the same in which read and write operations may be executed in the same clock cycle.
A further object of the invention is to provide a random access memory and method of operating the same in which read and write operations may be asynchronously enabled.
Yet another object of the invention is to provide such a random access memory and method of operating the same in which fully random addresses may be employed.
Still yet another object of the invention is to provide such a random access memory and method of operating the same in which successive and/or asserted addresses may be completely unrelated.
Another object of the invention is to provide such a random access memory and method of operating the same in which no restrictions are placed on successive and/or asserted addresses.
Another object of the invention is to provide such a random access memory and method of operating the same in which the same address may be used to read from and write to the memory in the same clock cycle.
A further object of the invention is to provide such a random access memory and method of operating the same in which a read/write control signal (e.g., a clock or control pulse) is the only control-type signal essential to operability.
Other objects and advantages of the present invention will become apparent from the following description, taken in connection with the accompanying drawings, wherein, by way of illustration and example, embodiments of the present invention are disclosed.
The present invention concerns a random access memory comprising: a write port comprising a set of data inputs and a write address bus, a read port comprising a set of data outputs and a read address bus, a read/write control signal configured to control data transfer operations at said write port and/or said read port in response to either (i) both rising and falling transitions or (ii) each of two logic levels of said read/write control signal, and a first random access memory array configured to store and/or retrieve data at a first random address in said first random access memory array defined by one or more signals on said write address bus and/or said read address bus.
In a further embodiment, the present invention concerns a process for reading data from and/or writing data to a random access memory array, comprising the steps of: (a) transferring a first plurality of data bits to or from a first random address in said random access memory array in response to a first transition of a read/write control signal, and (b) independently transferring a second plurality of data bits to or from a second random address in said random access memory array in response to a second transition of said read/write control signal.
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patent: 4752871 (1988-06-01), Sparks et al.
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patent: 5828606 (1998-10-01), Mick
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patent: 6094399 (2000-07-01), Mick
Arcoleo Mathew R.
Lovett Simon J.
Pancholy Ashish
Phelan Cathal G.
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Tran Andrew Q.
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