Random access memory device having inconsistent write-in and rea

Details Random access memory device having inconsistent write-in and rea Random access memory device having inconsistent write-in and rea

1995-08-14

1999-04-13

Hayes, Gail O.

Cryptography

Cryptanalysis

380 50, H04L 900

Patent

active

058945156

ABSTRACT:
A random access memory device having nonconforming write-in and read-out data is provided, and includes three major components: a random access memory (RAM) core, a control logic circuit, and a transfer device. The control logic circuit is responsive to a read/write signal, and a chip select signal for generating a write path enable signal, and read path enable signal. The transfer device is separated into a write path and a read path. The write path includes a write-transfer device and a tri-state buffer coupled in series. A data bus external to the memory device provides an input to the write path for write-in data, while the output of the write path is coupled to the RAM core input data. The read path includes a read transfer device coupled in series with a second tri-state buffer. The core output data from the RAM core is coupled to the read path as an input, while the output of the read path is coupled to the data bus external to the memory device. The read path and write path enable signals appropriately enable the read path and the write path for operation. The write-transfer device, and the read-transfer device operate in a noncomplementary fashion such that write-in data passing through the write-transfer device, and subsequently through the read-transfer device, is not restored to its original form, thus providing computer data protection.

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