Random access memory cell with different capacitor and transisto

Details Random access memory cell with different capacitor and transisto Random access memory cell with different capacitor and transisto

1976-09-13

1980-12-16

Davie, James W.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 23, 357 51, 357 91, 365149, 365182, H01L 2704, H01L 2978

Patent

active

042400929

ABSTRACT:
An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal silicon oxide which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3874955 (1975-04-01), Arita
J. E. Coe et al., "Enter the 16,384-bit RAM", Electronics, Feb. 19, 1976, pp. 116-120.
Chiu, "One-Device Memory Cell with Step Oxide Structure", IBM TDB, vol. 14, No. 11, Apr. 1972, pp. 3359-3360.
Abbas et al., "Memory Cell Structure", IBM TDB, vol. 18, No. 10, Mar. 1976, p. 3288.
Klepner, "One-Device Storage Cell with Implanted Storage Node", IBM TDB, vol. 19, No. 2, Jul. 1976.

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