Random access memory based space time switch architecture

Details Random access memory based space time switch architecture Random access memory based space time switch architecture

2008-01-01

2008-01-01

Patel, Jay K. (Department: 2616)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S395700, C370S429000

Reexamination Certificate

active

10210756

ABSTRACT:
A data switching circuit (10). The data switching circuit comprises at least one input (10in) for receiving during a same time period a plurality of data streams (ICH0-ICH127). Each of the data streams comprises a plurality of like-sized data quantities. The data switching circuit further comprises a plurality of addressable memories (10x), wherein each of the plurality of addressable memories comprises a plurality of memory cells. The data switching circuit further comprises circuitry (11) for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time. Lastly, the data switching circuit further comprises reading circuitry (13, 14), coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities to output channels.

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