Random access memory and linear interpolation circuit comprising

Details Random access memory and linear interpolation circuit comprising Random access memory and linear interpolation circuit comprising

1985-11-21

1989-06-20

Harkcom, Gary V.

Boots, shoes, and leggings

365190, 357 40, G06F 738, G11C 700, H01L 2702

Patent

active

048414620

ABSTRACT:
A random access memory (RAM) comprises memory cells each including an RS type flip-flop having complementary data inputs and transistors for forcing the flip-flop by that one of two data wires which is at a given level (high level for example) when a selection wire is at a first given level (high level for example). The flip-flop is connected to an output wire by circuitry for maintaining the output wire at the high level as long as the selection wire is at the first level and for causing the output wire to take the level corresponding to the condition of the flip-flop when the selection wire is brought to the other level. The transistors are preferably N-MOS for higher speed.

REFERENCES:
patent: 4282578 (1981-08-01), Payne et al.
patent: 4435793 (1984-03-01), Ochii
patent: 4511989 (1985-04-01), Sakamoto
patent: 4535426 (1985-08-01), Ariizumi et al.
patent: 4602545 (1986-07-01), Starkey
patent: 4635229 (1987-01-01), Okumura et al.
patent: 4653025 (1987-03-01), Minato et al.

Affiliated with

Also associated with

Rating

Random access memory and linear interpolation circuit comprising does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Random access memory and linear interpolation circuit comprising, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Random access memory and linear interpolation circuit comprising will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-530082