Ramped clock digital storage control

Details Ramped clock digital storage control Ramped clock digital storage control

2006-10-27

2009-11-24

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000, C327S210000

Reexamination Certificate

active

07622977

ABSTRACT:
Disclosed herein are digital systems and methods for use with a ramped clock signal. The digital system includes an input element having a data input to receive a data signal, a control input to receive a control signal, and a dynamic node to be driven by the ramped clock signal. The digital system further includes a static memory element having an input at the dynamic node and is configured to reside in an operational state in accordance with the data signal and the ramped clock signal. The input element further includes a switch coupled to the control input to condition updating of the operational state based on the control signal without decoupling the ramped clock signal from the dynamic node. In this way, distribution and delivery of the ramped clock signal to the digital system is continued to facilitate recovery of clock signal energy from the digital system.

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