Ramp gate erase for dual bit flash memory

Details Ramp gate erase for dual bit flash memory Ramp gate erase for dual bit flash memory

2008-01-15

2008-01-15

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140, C365S185330

Reexamination Certificate

active

07319615

ABSTRACT:
A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.

REFERENCES:
patent: 5608672 (1997-03-01), Tang et al.
patent: 6031766 (2000-02-01), Chen et al.
patent: 6331951 (2001-12-01), Bautista, Jr. et al.
patent: 6567316 (2003-05-01), Ohba et al.
patent: 6934194 (2005-08-01), Takahashi et al.
patent: 6944061 (2005-09-01), Camerlenghi et al.
patent: 6992938 (2006-01-01), Shubat et al.
patent: 7042766 (2006-05-01), Wang et al.
patent: 7072221 (2006-07-01), Wang
patent: 7113431 (2006-09-01), Hamilton et al.

Affiliated with

Also associated with

Rating

Ramp gate erase for dual bit flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ramp gate erase for dual bit flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ramp gate erase for dual bit flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2814018