RAM memory circuit and method for memory operation at a...

Details RAM memory circuit and method for memory operation at a... RAM memory circuit and method for memory operation at a...

2005-08-09

2005-08-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189020, C365S189050, C365S230020, C365S233100

Reexamination Certificate

active

06928024

ABSTRACT:
A RAM memory circuit has at least one memory bank with a multiplicity of memory cells arranged like a matrix in rows and columns and is subdivided into q≧2 areas, each of which comprises p≧1 segments each comprising a plurality of columns. Each segment is assigned a bundle of master data lines, which branches from an area bus assigned to the relevant area and, for its part, branches via a switching network to the memory cells of the relevant segment. The area buses can be connected cyclically to a common data port. In order to allow a read operation the beginning of which overlaps the end of a preceding write operation, each master data line bundle has coupled to it a data latch for holding the data respectively appearing there, and an isolating switch is in each case provided between each master data line bundle and the assigned area bus.

REFERENCES:
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5751656 (1998-05-01), Schaefer
patent: 6101135 (2000-08-01), Lee
patent: 6335901 (2002-01-01), Morita et al.
patent: 6556483 (2003-04-01), Ryan et al.
patent: 2001/0033522 (2001-10-01), Toda

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