Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2003-04-29
2004-11-23
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000, C365S196000, C365S203000, C365S230060
Reexamination Certificate
active
06822923
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a RAM memory circuit and method for controlling the RAM memory circuit having a multiplicity of memory cells and having addressing and control devices for accessing the memory cells for writing in and reading out data. The memory cells are disposed in a matrix form in rows and columns and each are addressed for the process of writing in or reading out a datum by activation of a word line associated with the relevant row and connection of a sense amplifier associated with the relevant column to a data path. A preferred area of application is dynamic RAMs (DRAMS), in particular, synchronous DRAMs (SDRAMs, DDR-RAMS or RDRAMs).
Dynamic random access memories, as are generally known by the acronym DRAM, contain one or more arrays or banks of memory cells that are in each case disposed in the manner of a matrix in rows and columns. Each row is assigned a row selection line, referred to as “word line” and each column is assigned a column selection line, which is referred to as “bit line” and is usually configured in two-core fashion (“bit line pair”). Each memory cell includes, in addition to a capacitor that forms the actual memory element and whose respective state “charged” or “uncharged” represents the binary or logic value “1” or “0” of the stored datum, a selection transistor that can be turned on by activation of the relevant word line. With the selection transistor in the on state, the capacitor is connected to the bit line pair to transfer the charge of the capacitor onto the bit line pair so that the stored datum can be sensed as a potential difference on the bit line pair. For sensing and evaluating the potential difference, each bit line pair is assigned a sense amplifier that is latched into a defined first or second state, depending on whether the sensed potential difference corresponds to the logic value “1” or “0” of the stored datum.
For a selective access to selected memory cells, first, a selected word line is activated by application of an activation potential (usually so-called “H” potential, which is positive with respect to the zero potential). The word line to be activated is selected depending on a row address provided, which is decoded in a row decoder. With the word line activation, the selection transistors of all the memory cells of the addressed row are turned on so that the potential differences that indicate all the data of the addressed row build up on the bit line pairs of all the columns. These data are latched in the assigned sense amplifiers. This latching operation has the effect that the sensed data are written back to the respective memory cells in amplified and, thus, refreshed form and, moreover, are ready for fetching in the sense amplifiers.
After this state has been reached, what conventionally follows is the further control of the DRAM for reading or writing, the sense amplifiers being selectively connected to a data path by actuation of selected transfer switches in order either to read out the latched data from the DRAM through the data path (read cycle) or to overwrite the data by new data (write cycle). This “column” selection is effected by selection of the transfer switches to be actuated depending on column select signals based upon column addresses that are decoded in a column decoder.
Starting from the command that initiates the activation of the selected word line, it takes a certain period of time for the sense amplifiers to reach their final state. First, it is necessary for the applied activation potential to develop along the word line until the selection transistors in the memory cells respond. Then a certain period of time elapses until the bit line pairs have accepted the charge of the memory cells and the sense amplifiers can be switched on to be driven into their latching state. Only afterward are the latched data released for read-out or overwriting. The minimum waiting time to be complied with between a word line activation command, and the start of each read or write cycle is defined in the context of the customary specification of a DRAM and, naturally, restricts the operating speed of the memory circuit.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a RAM memory circuit and method for controlling the RAM memory circuit that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that reduces the sum of the waiting times during the operation of a DRAM and, thereby, increases the average operating speed.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a RAM memory circuit, including a multiplicity of memory cells disposed in matrix form in rows and columns, the cells storing datum, the rows having row addresses, the columns having column addresses, word lines each being associated with a respective one of the rows, sense amplifiers each being associated with a respective one of the columns, data input/output means, a data path connected to the sense amplifiers and to the data input/output means for transferring data in either direction between the sense amplifiers and the data input/output means, each of the memory cells being addressable for writing in or reading out a datum by activation of the one word line associated with a respective one of the rows and by connecting a sense amplifier associated with a respective one of the columns to the data path, an addressing device having a row decoder connected to the word lines for selecting the word line to be activated dependent upon a provided row address and a column decoder connected to the sense amplifiers for selecting respective ones of the sense amplifiers to be connected to the data path dependent upon the column addresses provided thereto, and a control device connected to the word lines, the control device activating a selected one of the word lines and subsequently initiating a connection of the selected sense amplifiers to the data path, the control device, upon receiving an immediate-write command, being set to command a write operation to initiate a connection of the sense amplifiers selected by the column address provided to the data path at an instant t
a
+T
w
, where t
a
is an instant of an activation of the word line selected by the provided row address and T
w
is less than a charging time necessary, starting from the word line activation, to transfer the datum stored in one of the memory cells of the respective one of the rows to the respectively selected sense amplifier and to amplify the datum at the respectively selected sense amplifier.
Accordingly, the invention is realized on a RAM memory circuit that contains the following: a multiplicity of memory cells, which are disposed in matrix form in rows and columns and can each be addressed for the process of writing in or reading out a datum by activation of a word line assigned to the relevant row and connection of a sense amplifier assigned to the relevant column to a data path, an addressing device with a row decoder for the selection of the word line to be activated depending on a row address provided, and with a column decoder for the selection of the sense amplifiers to be connected to the data path depending on column addresses provided; a control device that is configured for the activation of the selected word line and for the subsequent initiation of the connection of the selected sense amplifiers to the data path. According to the invention, the control device can be set by an immediate-write command, which commands the write operation, such that it initiates the connection of the sense amplifiers selected by the column addresses provided to the data path at an instant t
a
+T
w
, where t
a
is the instant of the activation of the word line (WL) selected by the row address provided and T
w
is less than the charging time T
c
that is specific to the memory circuit and is necessary, starting from a word line activation, in order to transfer the datum stored i
Fischer Helmut
Pfeiffer Johann
Infineon - Technologies AG
Mayback Gregory L.
Nelms David
Pham Ly Duy
LandOfFree
RAM memory circuit and method for controlling the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with RAM memory circuit and method for controlling the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and RAM memory circuit and method for controlling the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3313471