Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-04-01
2003-04-15
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060, C365S189080
Reexamination Certificate
active
06549483
ABSTRACT:
This application claims priority from Canadian Patent application 2,342,516 filed Mar. 30, 2001 and Canadian Patent application 2,342,472 filed Mar. 30, 2001.
FIELD OF THE INVENTION
The present invention relates to semiconductor memories. In particular the invention relates to memory row decoders.
BACKGROUND OF THE INVENTION
DRAM memory cells consist of a single transistor and storage capacitor, where the storage capacitor can be formed as a planar, trench or stacked capacitor. DRAM memories are generally accessed by supplying a row address and a column address to access memory cells within the memory array. More specifically, the row address activates a selected wordline and the column address enables data to be transferred between selected complementary bitline pairs and a databus. The following description briefly highlights how memory cells are accessed in a memory array.
FIG. 1
shows a general block diagram of a DRAM of the prior art. Only the core circuits peripheral to the memory array are shown to simplify the schematic, however, those of skill in the art will understand that other DRAM circuits are required for its proper operation. DRAM
10
of
FIG. 1
includes a master row decoder
12
, row decoders
14
, bitline access circuit blocks
16
and memory array
18
. Bitline access circuit blocks
16
include bitline sense amplifiers, precharge circuits and column access devices. Memory array
18
consists of bitlines and wordlines, with memory cells located at the crossing points of the wordlines and bitlines. A detailed schematic of a memory array that can be used for memory array
18
is shown in FIG.
2
. In a read access operation for example, master row decoder
12
receives a portion of row address signals for generating predecoded row address signals used by row decoders
14
. Predecoding row address signals is typically done for selecting subsets of row decoders. In addition to receiving the predecoded row address signals, row decoders
14
receive another portion of row address signals for driving a selected wordline of memory array
18
. The bitline sense amplifiers of blocks
16
amplifies the voltage level of the bitlines after memory cell transistors are activated via the selected wordline. Column access devices of blocks
16
receive column address signals for coupling selected complementary bitlines to common databus DB. The number of column access devices activated by any one column address is determined by the configuration of the DRAM. For example, if the DRAM is configured to be a ×4 data width device, then memory array
18
provides four bits of data onto four complementary pairs of databuses in parallel. Those of skill in the art should understand that databus DB represents a predetermined number of pairs of complementary databus lines, and that the data width configuration of DRAM
10
is fixed.
FIG. 2
illustrates a well known arrangement of memory cells, wordlines and bitlines of memory array
42
in FIG.
1
. In this particular example four bitlines, ten wordlines labelled as WL to WL+9, and a corresponding number of memory cells are shown arranged in a folded bitline configuration. Each sense amplifier and column access block
31
is connected to a pair of complementary bitlines
30
/
32
labelled as BLi, BLi*, and
44
/
46
labelled as BLi+1, BLi+1*. Each wordline is driven by row decoders
14
of
FIG. 1
, and each individual sense amplifier and column access block
31
is part of a block
16
in FIG.
1
. It should be apparent to those of skill in the art that each block
31
also includes bitline precharge devices. Complementary bitlines
30
/
32
and
44
/
46
extend in parallel from one side of its respective sense amplifier and column access block
36
. Planar capacitor cells
36
are connected to each of the bitlines
30
and
32
via a respective bitline contact
42
. Bitlines
30
and
32
are typically formed of aluminum above the cells
36
and polysilicon wordlines
34
. Each cell
36
includes a cell plate diffusion, or active area
38
and an access transistor active area
40
. Polysilicon wordlines
34
run in a direction perpendicular to the bitline direction, and cross over access transistor diffusion areas
40
of any cell
36
in their path. Each cell
36
stores a single bit of data, represented as a voltage level stored on the storage capacitor. Single ended sensing is used to read out this data, in which a wordline such as WL is activated to couple a storage capacitor of a cell
36
to its corresponding bitline
32
. Since all complementary bitlines
30
/
32
and
40
/
46
are precharged to a mid-point voltage level, bitline
30
is used as a reference voltage level for the bitline sense amplifier of block
31
. The precharged voltage level of bitline
32
will change by a few hundred milli-volts when a cell
36
is coupled to it. Those of skill in the art will understand that the memory cells can also be trench or stacked capacitor DRAM cells.
The previously described read access operation is referred to as a random access operation if different wordlines are activated in each access cycle. However, an extension of the read access operation is a page mode read operation for successively reading and writing data to the memory at a faster rate than repeated random accesses. Most systems desire fast data access speeds to achieve faster overall system performance since memory access speeds tend to bottleneck system performance.
DRAM
10
is capable of operating in page mode, where data is successively accessed from the same activated wordline or row of memory array
18
. This means that a page of data can be accessed, where each page includes a finite number of words. For example, if memory array
18
provides an 8-bit wide word of data for each column address, and each column address can select one of four different words, then four words can be successively accessed in page mode operation. The advantage of page mode access is higher throughput of data than if the page was randomly accessed. Page mode access is well known in the art, and therefore does not require further discussion. Hence, page mode access is useful when a system needs to store and retrieve successive words of data quickly on the same page.
In the page mode discussion above, DRAM
10
was described as having an 8-bit data width. DRAM
10
can also be configured for 1, 4, 8 and 16 bit wide configurations for example. This is because different configurations are preferable for specific applications. These different configurations are permanently set by the manufacturer through bond options or fuses.
Some of the disadvantages with conventional DRAM memories are now discussed.
DRAM is susceptible to soft errors caused by alpha particle bombardment for example, which can unpredictably change the voltage level of the bitlines. Since the bitline sense amplifiers have low sensing margins to detect the few hundred milli-volt difference between the pair of complementary bitlines, alpha particle bombardment can cause misreads from the memory array. The effects of alpha particle bombardment could be reduced by increasing the sensing margin of the bitline sense amplifiers. DRAM also requires constant refreshing of its data in order to maintain its stored data due to inherent charge leakage of its storage capacitor. DRAM devices that require more frequent refreshing will consume more refresh power, which is exacerbated when the DRAM operates in abnormal voltage or temperature conditions. High power consumption due to refresh operations is undesirable, especially during a power down or sleep mode when the DRAM is not in use. Therefore, such DRAM's are not suitable for portable applications where power is limited.
The page length of the DRAM is set by the manufacturer and thus does not necessarily meet the requirements of a specific application. If the application requires access to a page of data greater than that provided by the DRAM, then a second page, or wordline, must be accessed. Activation of a second wordline introduces additional lat
Kowalczyk Dariusz
Kurjanowicz Wlodek
Popoff Greg
Wiatrowski Jacek
ATMOS Corporation
Borden Ladner Gervais LLP
Kinsman L. Anne
Phan Trong
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