RAM error correction using two dimensional parity checking

Details RAM error correction using two dimensional parity checking RAM error correction using two dimensional parity checking

1978-07-31

1980-01-15

Atkinson, Charles E.

Registers

Systems controlled by data bearing records

Time analysis

3401461AG, G06F 1110, G11C 2900

Patent

active

041834631

ABSTRACT:
An apparatus for and a method of providing error correction in a random access memory (RAM) using two dimensional parity checking. The RAM and a parity register are initialized such that the parity register represents the proper (i.e., either odd or even) longitudinal parity (i.e., parity for each individual bit position of all addressable locations) for the RAM. The parity register is updated each time an addressable location of the RAM is written into to maintain proper longitudinal parity. The horizontal or word parity of each addressable location is checked each time that addressable location is read. At the observance of improper word parity, a memory controller halts normal activity and recomputes the longitudinal parity by reading each addressable location of the RAM. A logical comparison (exclusive-or) of the current longitudinal parity at the time of observance of improper word parity with the recomputed longitudinal parity reveals the failing bit position. The memory controller corrects the failing bit position in the contents of the addressable location observed to have improper word parity and normal operation is resumed.

REFERENCES:
patent: 3242461 (1966-03-01), Silberg et al.
patent: 3629825 (1971-12-01), Bloom
patent: 3831144 (1974-08-01), En
patent: 3887901 (1975-06-01), Moore
patent: 4016409 (1977-04-01), Kim
patent: 4035766 (1977-07-01), Barker

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