RAM control device and memory device using the same

Details RAM control device and memory device using the same RAM control device and memory device using the same

2006-07-27

2010-11-30

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233110, C365S233140, C365S233150, C365S154000, C365S156000

Reexamination Certificate

active

07843762

ABSTRACT:
In a RAM control device, an arbiter circuit is means for generating BUSY1and BUSY2of exclusive logic with CLK1and CLK2so as to give a right to access RAM3to a host which has transmitted the first access clock and requesting a one-shot circuit to generate RAMCLK for deciding the timing to access the RAM3. The one-shot circuit is means for generating one pulse of RAMCLK with CLKRQ from the arbiter circuit and transmitting it to the RAM3. This configuration suppresses increase of the device size and cost and enables appropriate control of access to the RAM according to the access clocks of two systems inputted asynchronously.

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