Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-05-31
2003-07-22
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06598062
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to generating sum of products values and, more particularly, to a sum of products processing engine that employs random access memory for feedback purposes.
2. Discussion of the Related Art
In many digital signal processing applications, it is necessary to perform sum of products (SOP) computations. For example, in satellite communications systems it is common to use Discrete Fourier Transform (DFT) calculations to convert frequency modulated sampled waveforms into a format suitable for processing on a digital computer. Before a DFT can be performed on such incoming data, however, the data must be filtered in various different ways. Filter tap length (DFT size) refers to the number of clock cycles required to process one DFT, whereas the decimation factor refers to the number of clock cycles available to process one DFT. SOP circuits are particularly useful where the filter tap length is greater than the decimation factor resulting in a requirement for overlapping windows. The necessary data preparation techniques are done by a process commonly known as “window presumming.” Typical window presum algorithms involve the multiplication of the incoming data by known coefficient values and summing the product. The result is an SOP and is extremely common in the digital signal processing industry.
Many DSP techniques have evolved in an attempt to efficiently perform SOP calculations. A common problem with most architectures, however, is dealing with the difference in incoming data rates and available processing speeds. For example, most sampled waveforms are received at a rate much faster than a serial SOP processing engine can handle. Thus, a typical SOP processor will employ random access memory (RAM) intensive architectures to buffer the data for processing and multiple processing arms to create a parallel processing scheme. Such use of RAM, however, substantially increases overall memory size, increases processing latency, and reduces design scalability.
In one specific example, the SOP processor will include a ping-pong RAM at the input stage of the processor. Ping-pong RAMs employ an additional RAM as a buffer and the data is essentially “bounced” between the RAM's to create intended delays. The delayed data is then switched between a number of processing arms placed in parallel with one another. While this approach partially addresses processing speed issues, the aforementioned shortcomings remain. Thus, it is desirable to perform SOP calculations with minimal delay and memory use.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a processing engine for generating SOP values for incoming data is disclosed. In one embodiment, the processing engine includes a calculation module for generating intermediate and SOP values based on the incoming data and coefficient values, where the intermediate values are defined by product values and partial presum values. A feedback module stores the intermediate values until the calculation module generates SOP values. The processing engine further includes a reordering module for reordering the SOP values.
The feedback module includes a switching mechanism for retrieving intermediate values from the calculation module until the calculation module generates SOP values. Thus, a feedback RAM can store the intermediate values without the need for buffering RAM at the input stage. The feedback module further includes a holding register for retrieving the intermediate values from the feedback RAM, where the holding register routes the intermediate values to the calculation module.
A computerized method for generating SOP values is also provided. The method includes the step of storing product values in a feedback RAM as intermediate values until a predetermined number of product values is stored. Partial presum values are then stored in the feedback RAM as intermediate values until the calculation module generates SOP values, where the partial presum values are generated from the product values. The method further provides for reordering of the SOP values.
REFERENCES:
patent: 4573136 (1986-02-01), Rossiter
patent: 5410500 (1995-04-01), Ohki
patent: 5732251 (1998-03-01), Bartkowiak
patent: 5944775 (1999-08-01), Satoshi
Malzahn David H.
Miller, Esq. John A.
Northrop Grumman Corporation
Warn, Burgess & Hoffmann, P.C.
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