RAM addressing apparatus with lower power consumption and less n

Details RAM addressing apparatus with lower power consumption and less n RAM addressing apparatus with lower power consumption and less n

1993-03-31

1995-04-25

Harvey, Jack B.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395425, 365221, 36523003, 365239, G06F 1202, G11C 800

Patent

active

054106648

ABSTRACT:
An address converter that reduces the number of address bit changes between successive sequential addresses is provided to a RAM address bus for a sequentially accessed RAM. In the presently preferred embodiment, the address converter comprises a plurality of XOR gates for converting the access addresses into gray coded access addresses having at most one address bit change between successive access addresses. As a result, the power consumed and the noise generated over the address bus is reduced, thereby conserving power available and minimizing device package pins required by the digital system having the RAM and the RAM address bus.

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patent: 5115413 (1992-05-01), Sato et al.
patent: 5274788 (1993-12-01), Koike
patent: 5278962 (1994-01-01), Masuda et al.
patent: 5329629 (1994-07-01), Horst et al.

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