Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-02-28
2003-05-06
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C365S189090, C363S060000
Reexamination Certificate
active
06559710
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to Japanese Patent Application Number 2001-056114 filed Mar. 1, 2001, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a raised voltage generation circuit used for a semiconductor integrated circuit device. More specifically, the present invention relates to a raised voltage generation circuit used for a nonvolatile semiconductor memory device, and the like, which requires a voltage equal to or higher than a power source voltage, i.e., a raised voltage.
2. Description of the Related Art
In recent years, a power source voltage for a nonvolatile semiconductor memory device (a flash EEPROM) has been decreasing. In general, in order to decrease the power source voltage while maintaining fast access, a selected level of a voltage applied to a word line, which is coupled to a gate of a flash EEPROM cell, is raised to the level of the power source voltage or higher.
In the conventional art, a circuit for generating a raised voltage is well known.
FIG. 2
shows a typical raised voltage generation circuit
200
. Sources of p-type MOSFETs T
8
and T
9
are connected to power source voltage Vcc. A gate of the p-type MOSFET T
8
and a gate and drain of the p-type MOSFET T
9
are connected to a node N
7
. Thus, the p-type MOSFETs T
8
and T
9
form a current mirror circuit. The same amount of current flows through each of the p-type MOSFETs T
8
and T
9
. The node N
7
is also connected to a drain of an n-type MOSFET T
10
. Reference voltage Vref is output from a reference voltage generation circuit V
1
to a gate of the n-type MOSFET T
10
. On the other hand, voltage Vdiv is applied to a gate of an n-type MOSFET T
11
, which is paired with the n-type MOSFET T
10
. Voltage Vdiv is obtained by dividing raised voltage Vout, which is output from a charge pump circuit P
2
to an output node N
9
, using resistances R
3
and R
4
. A drain of a source-grounded n-type MOSFET T
12
is connected to sources of the n-type MOSFETs T
10
and T
11
. The n-type MOSFET T
12
performs power down control and source potential control of the n-type MOSFETs T
10
and T
11
. A capacitor C
2
, which is connected to an output of the charge pump circuit P
2
, smoothes a raised voltage before it is output from the raised voltage generation circuit
200
.
In the circuit described above, when the values of reference voltage Vref and divided voltage Vdiv are the same, the amount of current flowing through each of the n-type MOSFETs T
10
and T
11
are also the same. Thus, a state of equilibrium is achieved between the n-type MOSFETs T
10
and T
11
. However, for example, when raised voltage Vout, which is output from the charge pump circuit P
2
through an output node N
9
, is decreased, and divided voltage Vdiv becomes lower than reference voltage Vref, an amount of current flowing through the n-type MOSFET T
11
is decreased and the potential at a node N
8
, which connects a drain of the p-type MOSFET T
8
and a drain of the n-type MOSFET T
11
is increased. As a result, a charge pump circuit enable signal ENB, which is output from an inverter I
4
to which the potential at the node N
8
is input, goes to a low level, so that the operation of the charge pump circuit P
2
is activated. Alternatively, when raised voltage Vout at the node N
9
rises, and voltage Vdiv becomes higher than voltage Vref, an amount of current flowing through the n-type MOSFET T
11
is increased, and the potential at the node N
8
is decreased. As a result, the charge pump circuit enable signal ENB goes to a high level, and the operation of the charge pump circuit P
2
is stopped. In other words, the potential of the node N
8
is determined by a ratio of the currents flowing through the n-type MOSFETs T
10
and T
11
. The inverter I
4
performs operation control of the charge pump circuit P
2
in accordance with changes in potential at the node N
9
from the state of equilibrium so as to maintain output of the raised voltage Vout to be at an approximately constant potential.
There are various types of circuit arrangements for the reference voltage generation circuit V
1
for outputting reference voltage Vref. As an example of the reference voltage generation circuit V
1
,
FIG. 3
shows a reference voltage generation circuit including a pair of flash EEPROM cells (for example, floating-gate-type MOS transistors), which is disclosed in Japanese Laid-Open Publication No. 7-72944. Sources of p-type MOSFETs T
13
and T
14
are connected to output voltage Vout of a charge pump circuit P
3
. A gate and drain of the p-type MOSFET T
13
and a gate of the p-type MOSFET T
14
are connected to a node N
12
. In this structure, the p-type MOSFETs T
13
and T
14
together function as a current mirror circuit. The same amount of the current flows through each of the p-type MOSFETs T
13
and T
14
. Drains of the p-type MOSFETs T
13
and T
14
are respectively connected to drains of n-type MOSFETs T
15
and T
16
. Sources of the n-type MOSFETs T
15
and T
16
are respectively connected to drains of flash EEPROM cells F
3
and F
4
which have different amounts of charge stored in their floating gates. The n-type MOSFETs T
15
and T
16
decrease the voltage at the drains of the flash EEPROM cells F
3
and F
4
to 1 volt or lower. In this example, the voltage applied to each of the gates of the n-type MOSFETs T
15
and T
16
is
2
Vtn, which is twice as large as a threshold voltage of the n-type MOSFETs T
15
and T
16
. Sources of the flash EEPROM cells F
3
and F
4
are both connected to the ground potential. Reference voltage Vref, which is output from the reference voltage generation circuit V
1
, and a divided voltage at node N
10
, which is obtained by dividing reference voltage Vref using resistances R
5
and R
6
, are respectively applied to gates of the flash EEPROM cells F
3
and F
4
. The amount of charge stored in each of the flash EEPROM cells F
3
and F
4
is adjusted such that a state of equilibrium is achieved, i.e., the same amount of the current flows through each of the flash EEPROM cells F
3
and F
4
, when output voltage Vref is equal to a predetermined potential.
In such a circuit arrangement, when reference voltage Vref is low, the amount of current which flows through the flash EEPROM cell F
4
significantly decreases compared to the amount of current which flows through the flash EEPROM cell F
3
, and the voltage at the node N
11
rises. As a result, the voltage at the gate of the n-type MOSFET T
17
, whose threshold voltage is lower than that of a typical n-type MOSFET, is increased, and output voltage Vout of the charge pump circuit P
3
is supplied to reference voltage Vref. Alternatively, when reference voltage Vref is high, the amount of current flowing through the flash EEPROM cell F
4
significantly increases in comparison with the amount of current flowing through the flash EEPROM cell F
3
, and the potential at the node N
11
decreases. Thus, supply of Vout to Vref is interrupted by the n-type MOSFET T
17
. With such an operation, it is possible to maintain reference voltage Vref to be an approximately constant potential. As described above, the reference voltage generation circuit V
1
does not operate with a low voltage, and requires a voltage raised by the charge pump circuit P
3
as a power source.
There are various types of circuit arrangements for the charge pump circuit P
3
.
FIG. 4
shows a typical charge pump circuit. N-type MOSFETs T
18
, T
19
, and T
20
are connected in series. Gates of the n-type MOSFETs T
18
, T
19
, and T
20
are respectively connected to drains thereof, thereby acting as MOS diodes for preventing a backflow from source to drain. A P-type MOSFET T
21
receives the charge pump circuit enable signal ENB and supplies power source voltage Vcc to the n-type MOSFET T
18
. A capacitor C
3
is connected between a node N
15
and a node N
17
. The node N
15
is connected to the gate of the n-type MOSFET T
19
. The node N
17
is an output node of an in
Callahan Timothy P.
Englund Terry L.
Morrison & Foerster / LLP
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