Raised split gate EFET and circuitry

Details Raised split gate EFET and circuitry Raised split gate EFET and circuitry

1982-06-21

1986-03-04

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307584, 357 234, 357 238, 357 2314, 357 39, 357 43, 357 86, H03K 17687

Patent

active

045742081

ABSTRACT:
Lateral FET structure is disclosed for bi-directional power switching. A raised gate structure enables distal gate electrode portions to be in close proximity to FET channels and the remainder of the gate to be separated from the drift or drain region by a substantially greater distance so as to prevent undesired inducement of potential conduction channels through the drift region in the OFF state. This enables the gate to be referenced to the same potential level as one of the main terminals in the OFF state while still affording high voltage blocking capability. A multicell matrix array is also disclosed.

REFERENCES:
patent: 3450960 (1969-06-01), Chang et al.
patent: 4072975 (1978-02-01), Ishitani
patent: 4152714 (1979-05-01), Hendrickson et al.
patent: 4172260 (1979-10-01), Okabe et al.
patent: 4199774 (1980-04-01), Plummer
patent: 4414560 (1983-11-01), Lidow
J. Tihanyi, "Funct. Integ. of Power MOS and Bipolar Dev.," Conf. 1980 IEEE Iedm, Dec. 1980, pp. 75-78.
"A Parametric Study of Power MOSFETs", C. Hu, IEEE Electron Device Conference; Paper CH 1461-3/79, 0000-0385.
IEEE Transactions Electron Devices, vol. ED-25; #10; Oct., 1978.
"UMOS Transistors on (110) Silicon", Ammar & Rogers, Transactions IEEE; ED-27; May, 1980; pp. 907-914.

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