Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-09-10
2004-01-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S148000
Reexamination Certificate
active
06677789
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to charge pumps used in phase/delay-locked loops and deals more particularly with a charge pump having a linear time to charge transformation across the rail-to-rail voltage range.
BACKGROUND OF THE INVENTION
Digital frequency synthesizers have long been used in communication systems, particularly RF communications systems, to generate RF signals carried over RF channels. In frequency synthesis, it is desirable to achieve the selected frequency output with low phase noise in as little time as possible with any spurious output frequencies minimized. It is known to create a frequency synthesizer by placing a frequency divider function between the voltage-controlled oscillator (VCO) output and the phase frequency detector (PFD) in a phase-locked loop (PLL), wherein the VCO output frequency is an integer multiple of the input reference frequency to the PFD. The spurious outputs in question are usually associated with the charge pump in the PFD and occur at the phase detector operating frequency, which is generally the same as channel spacing. Incorporating the fractional-N division function in the PLL allows the phase detector to operate at a much higher frequency for the same channel spacing and have better phase noise, however, the fractional-N division function also introduces fractional spurs at the fractional offset and fractions of the comparison frequency.
A functional block diagram of a representative phase-locked loop frequency synthesizer having a frequency divider function in the feedback loop between the VCO output and the phase detector is illustrated in FIG.
1
and generally designated
10
. The phase-locked loop frequency synthesizer
10
is a general class known as Integer-N phase-locked loop frequency synthesizers. A reference frequency (F
IN
) from a frequency generator source
12
is applied to the input
14
of a frequency reference divider
16
. The reference divider
16
generates the desired reference frequency F
REF
at its output
18
, which is coupled to one input
20
of a phase frequency detector (PFD)
22
. A divide-by-N counter
50
located in the feedback path between the VCO output
48
and an input
24
of the PFD
22
provides the desired fractional division function. The PFD
22
has an UP output
26
and a DOWN output
22
coupled to the UP input
32
and DOWN input
34
, respectively, of the charge pump
30
which is shown separately from the PFD
22
for purposes of clarity and to give a better understanding of the invention. The charge pump
30
responds to the UP or DOWN input signal from the PFD
22
to supply or sink current at its output
36
, which output
36
is coupled to the input
38
of the loop filter
40
. The output
42
of the loop filter
40
is coupled to the input
44
of the VCO
46
to provide control to the VCO to cause it to generate the desired output frequency F
OUT
at its output
48
. The signal F
COMP
at the output
54
of the divide-by-N counter
50
is coupled to the input
24
of the PFD
22
and is representative of the loop phase error, that is, the difference in phase between the frequency F
OUT
at the VCO output
48
and the input frequency F
REF
at the input
20
to the PFD
22
. The operation of Integer-N phase locked loops of the general type described above wherein a charge pump sources or sinks current to or from the loop filter is well known to those skilled in the art. It will also be understood by those skilled in the art that a charge pump sources or sinks current to or from the loop filter in a similar manner in fractional-N phase locked loops. The reader
20
is referred to textbooks and readily available commercial literature to gain a fuller understanding of the operation of such PLLs.
As frequency synthesizers operate at increasingly faster or higher speeds due to the continuous advances made in semiconductor processes, which processes have provided for improved component matching and performance, there has been a need to improve the performance and linearity of charge pumps used to drive the loop filter in a phase-locked loop. One approach to improve performance has been to use a cascoded current mirror as illustrated in
FIG. 2
to achieve matching at the output. By definition a linear timing error-to-voltage correction will be needed when the reference frequency F
REF
is compared to the divided VCO frequency F
COMP
. A linear timing error-to-voltage correction is achieved by ensuring that for all voltages there is a constant current flowing into a known capacitance as in the case of the loop filter in the phase-locked loop. As semiconductor fabrication techniques improve to operate with lower voltage power sources, it is necessary to provide more output current for a given die size and to maintain precise regulation of the current. A typical prior art rail-to-rail charge pump is represented by the electrical circuit schematic diagram shown in FIG.
2
and is generally designated
100
. The charge pump
100
includes cascoded current mirrors in an attempt to achieve matching for linear operation. In the rail-to-rail cascaded current mirrors circuit shown in
FIG. 2
, the sink and mirroring devices must be very closely matched for balancing. When switches S
1
and S
2
operate due to the PFD generating an UP signal, current flows from rail VDD through P
1
and P
4
and is mirrored in P
3
and P
6
, respectively. Current through P
3
and P
6
is delivered to the V
CAP
NODE at the charge pump output
102
to charge or source current to the end
104
of the loop filter capacitor generally designated
106
, that is, increase the voltage across the loop filter capacitor. The end
108
of the loop filter capacitor
106
opposite the V
CAP
NODE output
102
is connected to the rail VSS.
When switches S
3
and S
4
operate due to the PFD generating a DOWN signal, current flowing through N
7
and N
9
is mirrored in N
8
and N
10
, respectively, to sink current from the V
CAP
NODE at the charge pump output
102
to discharge the loop filter capacitor
106
, that is, to lower the voltage across the loop filter capacitor. When switches S
3
and S
4
are operated, switches S
1
and S
2
are open, and the current flowing through P
1
and P
4
is mirrored in P
2
and P
5
, respectively. The current through P
2
and P
5
flows through N
7
and N
9
to the rail VSS.
I
REF
is a current source. If the sink and mirroring devices are not precisely matched, the current supplied to and sunk from the V
CAP
NODE at the charge pump output
102
will not have a linear response, that is, the loop filter capacitor
106
may charge and discharge at different rates from the same number of UP signal and DOWN signal pulses from the PFD. This causes the voltage at the V
CAP
NODE to vary over time during the charging and discharging of the loop capacitor, which results in reference spurs for integer PLLs and fractional and offset spurs for fractional PLLs and a nonlinear time-to-charge transformation.
The prior art cascoded current mirror charge pump of
FIG. 2
also has limitations on the switching speed of switches S
1
, S
2
and S
3
, S
4
due to the characteristics of transistor devices P
3
, P
6
and N
8
, N
10
. The transistors P
3
, P
6
and N
8
, N
10
are of relatively large size in the range of L=1 &mgr;m and W=1000 &mgr;m which causes the devices to act or function as large capacitors. Any differences in switching times between switches S
1
, S
2
or S
3
, S
4
cause the transistor device to discharge during the switching time interval difference, that is, one transistor is switched fully ON or OFF before the other transistor is switched fully ON or OFF. It is this discharge caused by the switching time difference that controls the maximum switching frequency of the switches. The cascoded transistors and additional transistor switch limit the range of the voltage on V
CAP
NODE at the charge pump output
102
due to the voltage drops across the devices.
Accordingly, it is an object of the present invention to provide a linear rail-to-rai
Lam Tuan T.
Ware Fressola Van Der Sluys & Adolphson LLP
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