Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2003-12-31
2004-08-31
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S128000, C341S155000, C341S118000
Reexamination Certificate
active
06784823
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention generally relates to a dual slope analog to digital converter, and more particularly to a dual slope analog to digital converter providing rail to rail input voltage range and finer resolution.
2. Description of Related Art
A conventional dual slope analog to digital converter (ADC) is illustrated in FIG.
1
. According to the circuit, the input voltage range is narrow. For example, in the case that the input transistor pair of the input operational amplifier (OPAMP)
301
is NMOS, the input range of the OPAMP is from about 1V to VDD. In the case of the mobile application product or LSI using advanced process technology, the power supply voltage VDD is usually low, ranging from 1.5V to 3V. This makes the range of input voltage narrow, causing it difficult to get enough resolution of ADC. Thus a dual slope ADC with rail to rail (VSS to VDD) input range is desired.
SUMMARY OF INVENTION
An object of the present invention is to provide rail to rail input range, a minor error and finer resolution of ADC.
Another object of the present invention is to provide a dual slope ADC with a single pin external capacitor connection.
The dual slope ADC circuit scheme of this present invention includes an input stage, an integrator stage, and a comparator stage. For the input stage, the circuit is composed of a first operational amplifier (OPAMP). The input voltage is stored in a first capacitor, which is connected in negative feedback loop fashion of the first OPAMP, and this voltage is then applied between the output terminal and the negative input of the first OPAMP. The first OPAMP keeps the voltage of the positive input to be the same as the negative input of which. The current flowing through a first resistor is linearly proportional to the input voltage, where the first resistor couples the output of the first OPAMP and a second OPAMP, which is part of the integrator. The second OPAMP and a second capacitor work as an integrator to charge the current from the resistor, where the second capacitor is connected in negative feedback loop fashion of the second OPAMP. The comparator stage, comprising a third OPAMP, checks the voltage across the second capacitor. A third capacitor coupling to the negative input terminal of the second OPAMP compensates the offset voltages of the first OPAMP. On the other hand, a plurality of switches are controlled to make the necessary connections for the different operation phases, including offset cancellation phase, integration phase, discharge phase, and charge reset phase. The phases are described as follows.
The offset cancellation phase of the rail to rail dual slope ADC of this present invention is described herein. At a stable state, the voltage across the first resistor becomes zero, the voltage across the third capacitor is equal to the offset voltage of the first OPAMP, the negative input of the second OPAMP is determined by an analog ground voltage (AGND) and the offset voltage of the second OPAMP, and the positive input of the third OPAMP is determined by the output voltage and the offset voltage of the third OPAMP.
The integration phase of the rail to rail dual slope ADC of this present invention is described herein. The voltage across the first resistor is the input voltage VIN. The current through the first resistor charges the second capacitor and the output voltage of the second OPAMP decrease constantly if VIN is positive.
The discharge phase of the rail to rail dual slope ADC of this present invention is described herein. The voltage across the first resistor is the input voltage Vref, which is a predetermined constant voltage. The current through the first resistor discharges the second capacitor and the output voltage of the second OPAMP increase constantly if Vref is minus. The output voltage of the third OPAMP changes from low to high, when the output voltage of the second OPAMP across the initial voltage, which is determined after the offset cancellation phase. This change of the output voltage of the third OPAMP indicates the completion of the discharge phase.
The charge reset phase of the rail to rail dual slope ADC of this present invention is described herein. In this phase, unnecessary residual charge in the second capacitor is discharged to the initial voltage,which is determined after the offset cancellation phase. The difference from the offset cancellation phase is that the charge reset phase can discharge the unnecessary charge in the second capacitor more quickly than the offset cancellation phase. Although the charge reset phase has the similar function as the offset cancellation phase, the offset cancellation is still necessary to refresh the voltage across the third capacitor.
Accordingly, the present invention has wider input voltage range than the conventional scheme, since the input voltage range of the present invention is rail to rail (from VSS to VDD) whereas that of the conventional scheme is about from 1V to VDD. For example, if VDD is 1.5V, the input voltage range of the conventional scheme is only 0.5V, while the input voltage range of the present invention is 1.5V, which consequently is able to provide finer resolution of ADC.
Moreover, since the input voltage of the first OPAMP is kept around AGND, the offset voltage of the first OPAMP is not affected by the input voltage, and a minor error and finer resolution are obtained in this present invention.
A simplified scheme of the rail to rail dual slope ADC of this present invention is described herein. In this configuration, there is no integrator OPAMP. Instead, the current flowing through the first resistor charges an external capacitor through single pin. The operation of the circuit is similar to that with integrator. The difference is that the voltage of the positive input of the first OPAMP changes according to the terminal voltage of the external capacitor in the integration phase and the discharge phase. This change of the positive input of the first OPAMP reduces the input voltage range. Since the circuit is configured with single pin capacitor connection, this circuit is exemplary useful for applications that do not require high resolution but requiretemptemp small pin count and simple circuit. Notice that this circuit is applied to a VCO as an example.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.
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Jianq Chyun IP Office
Nguyen Linh V.
Tokar Michael
Winbond Electronics Corp.
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